From patchwork Thu Jan 26 13:52:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1732290 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=bAvDSRmB; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P2hyC3B04z23hg for ; Fri, 27 Jan 2023 00:53:55 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pL2gB-0003es-Ac; Thu, 26 Jan 2023 08:52:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL2g4-0003ci-FA for qemu-devel@nongnu.org; Thu, 26 Jan 2023 08:52:33 -0500 Received: from mail-ot1-x330.google.com ([2607:f8b0:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pL2g1-00043f-Jc for qemu-devel@nongnu.org; Thu, 26 Jan 2023 08:52:32 -0500 Received: by mail-ot1-x330.google.com with SMTP id e21-20020a9d5615000000b006884e5dce99so817325oti.5 for ; Thu, 26 Jan 2023 05:52:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mxEbgjU5aR+oYquuJNQfmH8bDfSRZI4C/R+GpocfbUU=; b=bAvDSRmBFUuJkmr4IsvIij0ABtll3YYYB/6wTXyyku/jVNEdS/8QKX/dhEkn3mlij5 KxIdRClG/LSNDRfwHLtzvTvt/GZqrAJypwSKwAY4OJUskXfwDqsnZoCndXuFsiNZQYE5 3pu8daJDu1r8RUumLWmYFmdA7pxgjqqPisUqWwKby9kfi/Z4ROCac+VAb2tMWG3uOky2 t68RMzdjhUZI6lWncEXvmwBA4pFQQ9x/8x2Fq7YFwHKYW0lryG8NPY4+HKuC1/jYvZN9 jbBnp/GIaGHH0SwEnfuhXV2sev3HD5B4IVR+zbuEUHKmHPDyHXai5XrpFke8OsO3Ay83 LYVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mxEbgjU5aR+oYquuJNQfmH8bDfSRZI4C/R+GpocfbUU=; b=a0dL4yfAUhvobQVHe3r5qFQLBbJF74DgOiyuJHnoRpasO00FE/e0z4LE8q0zgkE2gt ZX3ARXBZrlJADpFEf7GctjW7+45s4AawQTBH96CFp7Sqyb1ftxSdZZ4omzC6zoOAas4M qatGNhZrwhdMlipN0IaAuIMUDe6uz8JysO3DytBCAsJjx7Xjugdysyx5LMOMGP+zdSut ZeOA7V/KPfP8xlH2f/xq5cdV0VSupfldBLfGSdRZ5GcRsVz4i0NhcQUAIwtF9AybXgbO I5IO5tWF3i8Jve7K3yiscAuI1TOA3P80rz3w5ThB/kFKN2nTwI4lOF+TdICzvKeT8p86 PLqw== X-Gm-Message-State: AO0yUKXNIKTm4x2vuB9Pi6OIflTMS6o0Dt+7w6HQL50MmIZR/SbbAZOA 5C66koTuxZbnQ+ExbqUslYiYaNVqoX6tjrj9SA8= X-Google-Smtp-Source: AK7set/k15wnJxSWRgAyFRWeZR7ga6ybjDtDjFSyKgTKNCavX825cV1qqIhzP+u4p7YCOKLPqOa8pQ== X-Received: by 2002:a9d:174:0:b0:686:4528:8b9a with SMTP id 107-20020a9d0174000000b0068645288b9amr1078715otu.13.1674741147487; Thu, 26 Jan 2023 05:52:27 -0800 (PST) Received: from grind.dc1.ventanamicro.com (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id w19-20020a9d77d3000000b00661b46cc26bsm496323otl.9.2023.01.26.05.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 1/3] hw/riscv/boot.c: calculate fdt size after fdt_pack() Date: Thu, 26 Jan 2023 10:52:17 -0300 Message-Id: <20230126135219.1054658-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126135219.1054658-1-dbarboza@ventanamicro.com> References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org fdt_pack() can change the fdt size, meaning that fdt_totalsize() can contain a now deprecated (bigger) value. Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 3172a76220..a563b7482a 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -287,8 +287,13 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; hwaddr dram_end = dram_base + mem_size; - int ret, fdtsize = fdt_totalsize(fdt); + int ret = fdt_pack(fdt); + int fdtsize; + /* Should only fail if we've built a corrupted tree */ + g_assert(ret == 0); + + fdtsize = fdt_totalsize(fdt); if (fdtsize <= 0) { error_report("invalid device-tree"); exit(1); From patchwork Thu Jan 26 13:52:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1732291 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com header.a=rsa-sha256 header.s=google header.b=A3GD4qNs; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4P2hyF0mbjz23hg for ; Fri, 27 Jan 2023 00:53:57 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pL2gB-0003en-5G; Thu, 26 Jan 2023 08:52:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL2g5-0003cn-2n for qemu-devel@nongnu.org; Thu, 26 Jan 2023 08:52:33 -0500 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pL2g3-000447-8O for qemu-devel@nongnu.org; Thu, 26 Jan 2023 08:52:32 -0500 Received: by mail-oi1-x230.google.com with SMTP id r9so1395190oie.13 for ; Thu, 26 Jan 2023 05:52:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J7bp6OWxKmqGSF5SEiZBAGPU/QdVvSpCmmITMPl8D0o=; b=A3GD4qNst3zaCM83QgWFYix9P0svsdTKPmsLQda1l2A0BUp4oh9URMUY97crsS6c2X 4GU83PFNonO2DlHOoaaT/LId7cRxblEuziOXNKCBm2oxpmeEDujdvdmMm6Eggs0inESZ ARrVhOGykRAVvgEyanKZ9fu/0ZiDaKC2yYNOgmrkvZbTs4LJivs4TqIjjtRa1Pq+Q6/V R1fUZxIhMVKWvrrT8gb66WGuY9dLjlA5/HOEWcLN33M9WCWM1thoZBPsFZXEentVaii7 LdmkIBgMFBxVRBMNDifruXv0VyX/DWckj4y0Bl8kfIckkq7s53Yg5Xsbwx2d8OKoN6Kj heyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J7bp6OWxKmqGSF5SEiZBAGPU/QdVvSpCmmITMPl8D0o=; b=RCBJXxJDjH4/I0d4FLWMFOri3/AsM6dTCkLQHaG5TP0ZOF+aM8zzFtoSxhj6H/k9bE /gDOXHUJYmmti63+b8N1Sk7HNCnouZcs7WQ9wjHGp3MaO4HHEcK7MwW65k0EjTM9o6F5 metDuRKDAIW8Sb8HVON2XiOl9Q+tnq6jizz/Ndg3jkUJCmZfP1k2bF2N+kUW+i/RJFAm iLaF9ET0YQWBxhNAKcWugIGhA5bmxzUy6PD6X5OAtUu3RfNOKWWf6KlPHne6FDh09Jg+ it9ibFx8J6Dm1PbYOZWSJZtWoXPdeso5tUpvuTAOu0CVB/C1VNca+ez1cXpRsvy/J6c8 B9Tg== X-Gm-Message-State: AFqh2kqPqMxhp17bdBA2DG24uEpnb0IV3jhxjJhiUnMUWJIkIZGU0YOM hQtlNHtrb5N1Sf0ahSTlEvBWGNAaOUOfM2OIsR8= X-Google-Smtp-Source: AMrXdXvt6pffvoqelaHZVawGGcMmL3SdAa+ScoInhgFypDphwdebx62VyQkYslawKHdevQrcm4goUQ== X-Received: by 2002:a54:4195:0:b0:35e:1a0f:7dc0 with SMTP id 21-20020a544195000000b0035e1a0f7dc0mr14207849oiy.8.1674741149532; Thu, 26 Jan 2023 05:52:29 -0800 (PST) Received: from grind.dc1.ventanamicro.com (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id w19-20020a9d77d3000000b00661b46cc26bsm496323otl.9.2023.01.26.05.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 2/3] hw/riscv: split fdt address calculation from fdt load Date: Thu, 26 Jan 2023 10:52:18 -0300 Message-Id: <20230126135219.1054658-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126135219.1054658-1-dbarboza@ventanamicro.com> References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org A common trend in other archs is to calculate the fdt address, which is usually straightforward, and then calling a function that loads the fdt/dtb by using that address. riscv_load_fdt() is doing a bit too much in comparison. It's calculating the fdt address via an elaborated heuristic to put the FDT at the bottom of DRAM, and "bottom of DRAM" will vary across boards and configurations, then it's actually loading the fdt, and finally it's returning the fdt address used to the caller. Reduce the existing complexity of riscv_load_fdt() by splitting its code into a new function, riscv_compute_fdt_addr(), that will take care of all fdt address logic. riscv_load_fdt() can then be a simple function that just loads a fdt at the given fdt address. We're also taken the opportunity to clarify the intentions and assumptions made by these functions. riscv_load_fdt() is now receiving a hwaddr as fdt_addr because there is no restriction of having to load the fdt in higher addresses that doesn't fit in an uint32_t. Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 33 +++++++++++++++++++++++++-------- hw/riscv/microchip_pfsoc.c | 6 ++++-- hw/riscv/sifive_u.c | 7 ++++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/boot.h | 4 +++- 6 files changed, 43 insertions(+), 20 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index a563b7482a..a6f7b8ae8e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -283,9 +283,21 @@ out: return kernel_entry; } -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +/* + * The FDT should be put at the farthest point possible to + * avoid overwriting it with the kernel/initrd. + * + * This function makes an assumption that the DRAM is + * contiguous. It also cares about 32-bit systems and + * will limit fdt_addr to be addressable by them even for + * 64-bit CPUs. + * + * The FDT is fdt_packed() during the calculation. + */ +uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, + void *fdt) { - uint64_t temp, fdt_addr; + uint64_t temp; hwaddr dram_end = dram_base + mem_size; int ret = fdt_pack(fdt); int fdtsize; @@ -306,11 +318,18 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) * end of dram or 3GB whichever is lesser. */ temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); - ret = fdt_pack(fdt); - /* Should only fail if we've built a corrupted tree */ - g_assert(ret == 0); + return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); +} + +/* + * 'fdt_addr' is received as hwaddr because boards might put + * the FDT beyond 32-bit addressing boundary. + */ +void riscv_load_fdt(hwaddr fdt_addr, void *fdt) +{ + uint32_t fdtsize = fdt_totalsize(fdt); + /* copy in the device tree */ qemu_fdt_dumpdtb(fdt, fdtsize); @@ -318,8 +337,6 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) &address_space_memory); qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); - - return fdt_addr; } void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index b7e171b605..a30203db85 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr, true, NULL); /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* Load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b0b3e6f03a..6bbdbe5fb7 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -608,9 +608,10 @@ static void sifive_u_machine_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 483581e05f..ceebe34c5f 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,9 +316,9 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 48326406fd..43fca597f0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1292,9 +1292,10 @@ static void virt_machine_done(Notifier *notifier, void *data) start_addr = virt_memmap[VIRT_FLASH].base; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index bc9faed397..7babd669c7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,7 +48,9 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, + void *fdt); +void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, hwaddr rom_base, hwaddr rom_size, From patchwork Thu Jan 26 13:52:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 1732284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[200.148.13.157]) by smtp.gmail.com with ESMTPSA id w19-20020a9d77d3000000b00661b46cc26bsm496323otl.9.2023.01.26.05.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics Date: Thu, 26 Jan 2023 10:52:19 -0300 Message-Id: <20230126135219.1054658-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126135219.1054658-1-dbarboza@ventanamicro.com> References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a mem_size (which is defaulted to MachineState::ram_size in all boards) and the FDT pointer. And it makes a very important assumption: the DRAM interval dram_base + mem_size is contiguous. This is indeed the case for most boards that uses a FDT. The Icicle Kit board works with 2 distinct RAM banks that are separated by a gap. We have a lower bank with 1GiB size, a gap follows, then at 64GiB the high memory starts. MachineClass::default_ram_size for this board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM size, meaning that there we'll always have at least 512 MiB in the Hi RAM area. Using riscv_compute_fdt_addr() in this board is weird because not only the board has sparse RAM, and it's calling it using the base address of the Lo RAM area, but it's also using a mem_size that we have guarantees that it will go up to the Hi RAM. All the function assumptions doesn't work for this board. In fact, what makes the function works at all in this case is a coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put the FDT under a 3Gb address, which happens to be exactly at the end of DRAM_LO. If the base address of the Lo area started later than 3Gb this function would be unusable by the board. Changing any assumptions inside riscv_compute_fdt_addr() can also break it by accident as well. Let's change riscv_compute_fdt_addr() semantics to be appropriate to the Icicle Kit board and for future boards that might have sparse RAM topologies to worry about: - relieve the condition that the dram_base + mem_size area is contiguous, since this is already not the case today; - receive an extra 'dram_size' size attribute that refers to a contiguous RAM block that the board wants the FDT to reside on. Together with 'mem_size' and 'fdt', which are now now being consumed by a MachineState pointer, we're able to make clear assumptions based on the DRAM block and total mem_size available to ensure that the FDT will be put in a valid RAM address. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 38 ++++++++++++++++++++++++++------------ hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 3 ++- include/hw/riscv/boot.h | 4 ++-- 6 files changed, 36 insertions(+), 18 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index a6f7b8ae8e..8f4991480b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -284,33 +284,47 @@ out: } /* - * The FDT should be put at the farthest point possible to - * avoid overwriting it with the kernel/initrd. + * This function makes an assumption that the DRAM interval + * 'dram_base' + 'dram_size' is contiguous. * - * This function makes an assumption that the DRAM is - * contiguous. It also cares about 32-bit systems and - * will limit fdt_addr to be addressable by them even for - * 64-bit CPUs. + * Considering that 'dram_end' is the lowest value between + * the end of the DRAM block and MachineState->ram_size, the + * FDT location will vary according to 'dram_base': + * + * - if 'dram_base' is less that 3072 MiB, the FDT will be + * put at the lowest value between 3072 MiB and 'dram_end'; + * + * - if 'dram_base' is higher than 3072 MiB, the FDT will be + * put at 'dram_end'. * * The FDT is fdt_packed() during the calculation. */ -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, - void *fdt) +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, + MachineState *ms) { - uint64_t temp; - hwaddr dram_end = dram_base + mem_size; - int ret = fdt_pack(fdt); + int ret = fdt_pack(ms->fdt); + hwaddr dram_end, temp; int fdtsize; /* Should only fail if we've built a corrupted tree */ g_assert(ret == 0); - fdtsize = fdt_totalsize(fdt); + fdtsize = fdt_totalsize(ms->fdt); if (fdtsize <= 0) { error_report("invalid device-tree"); exit(1); } + /* + * A dram_size == 0, usually from a MemMapEntry[].size element, + * means that the DRAM block goes all the way to ms->ram_size. + */ + if (dram_size == 0x0) { + dram_end = dram_base + ms->ram_size; + } else { + dram_end = dram_base + MIN(ms->ram_size, dram_size); + } + /* * We should put fdt as far as possible to avoid kernel/initrd overwriting * its content. But it should be addressable by 32 bit system as well. diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index a30203db85..e81bbd12df 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -634,7 +634,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + memmap[MICROCHIP_PFSOC_DRAM_LO].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); /* Load the reset vector */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6bbdbe5fb7..ad3bb35b34 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -609,7 +609,8 @@ static void sifive_u_machine_init(MachineState *machine) } fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + memmap[SIFIVE_U_DEV_DRAM].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ceebe34c5f..b5979eddd6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -317,7 +317,8 @@ static void spike_board_init(MachineState *machine) } fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + memmap[SPIKE_DRAM].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 43fca597f0..f079a30b60 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1293,7 +1293,8 @@ static void virt_machine_done(Notifier *notifier, void *data) } fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + memmap[VIRT_DRAM].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 7babd669c7..a6099c2dc6 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,8 +48,8 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, - void *fdt); +hwaddr riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, + MachineState *ms); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr,