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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id cx16-20020a05640222b000b0046b9c536fc5sm3458151edb.63.2022.12.08.07.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Dec 2022 07:12:04 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Palmer Dabbelt , Alistair Francis , Bin Meng , Philipp Tomsich , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [RFC PATCH] RISC-V: Save mmu_idx using FIELD_DP32 not OR Date: Thu, 8 Dec 2022 16:11:59 +0100 Message-Id: <20221208151159.1155471-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Christoph Müllner Setting flags using OR might work, but is not optimal for a couple of reasons: * No way grep for stores to the field MEM_IDX. * The return value of cpu_mmu_index() is not masked (not a real problem as long as cpu_mmu_index() returns only valid values). * If the offset of MEM_IDX would get moved to non-0, then this code would not work anymore. Let's use the FIELD_DP32() macro instead of the OR, which is already used for most other flags. Signed-off-by: Christoph Müllner Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 278d163803..d68b6b351d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -80,7 +80,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags |= TB_FLAGS_MSTATUS_FS; flags |= TB_FLAGS_MSTATUS_VS; #else - flags |= cpu_mmu_index(env, 0); + flags = FIELD_DP32(flags, TB_FLAGS, MEM_IDX, cpu_mmu_index(env, 0)); + if (riscv_cpu_fp_enabled(env)) { flags |= env->mstatus & MSTATUS_FS; }