From patchwork Sun Oct 16 12:27:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1690377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=IP0zpxt9; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Mqzxw6K7jz23jf for ; Sun, 16 Oct 2022 23:31:16 +1100 (AEDT) Received: from localhost ([::1]:50782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ok2nS-0003Db-M9 for incoming@patchwork.ozlabs.org; Sun, 16 Oct 2022 08:31:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ok2kp-0002N3-BM; Sun, 16 Oct 2022 08:28:31 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:34646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ok2km-0000Ov-Uf; Sun, 16 Oct 2022 08:28:31 -0400 Received: by mail-ej1-x62d.google.com with SMTP id ot12so19484645ejb.1; Sun, 16 Oct 2022 05:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7YchITTcnUYZ4WJgcEjOn1WReqvfHLeSxHYKWWHpblk=; b=IP0zpxt9G8jSSrBk2LYX9rA1kWXXYZ9bf9SND67EEULKT4tUQ+yBYkX9Myp3BnC/Hw 3ripGqQzgN2oG1MvvPnI13vNgn4zijnmMyz6n77MmH8JB2azD2h1b0AZ3UEteVt9WnIX geFv806QnCjEUqMENIcjLYiHhOStPw8VEH+ag0y2KRi7Jwqzd2pbuWqHh7/HqO5audBj S7YGIiqm6XesPfbUzf9hjuhOwQW4JHTFjSsGj+vzMWqCW6yfXoCi+D4E66jPgX+Sbwca fj+Lf3q3Lz0piTG2miiV7UPZHILb+/kJxS43PzTNbUTtHbalJqvQ20WIJZSsqFinRNAu en0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7YchITTcnUYZ4WJgcEjOn1WReqvfHLeSxHYKWWHpblk=; b=1pXxFEGE4RK22gx+B96ZkZQAvglUqva8O5QGF4n+T5J+e6O2bBiF7jYj3bl01yhhsn EY3NcScEDCRHoCZw2JK3K0nLgilZoScnxIYZxitVkLfo4GOUaRAbtrEywtyh4Hyo8gaL QxketiKCoIE/YGKx5JsjGnARvJFQwzbbL3It1A6scJMLtUNQxGMoRo48qcSdGH3gpl5+ Ov7f7lHSqMTa/2ZsKuYKcK5aVNyekY/WZqmMIWpr52L9kBYtyK+M118R2aiaOOQzTQ9F eE25asvfmJlEMsjnTbn77doBiFb+ukMKkEz6lB92bHgTod2Tbb8ASv9REgdf1qGjMSxu bSuA== X-Gm-Message-State: ACrzQf3avqI3BuqtKVL5YUJ96WMKpNFKGlVGwzieaWPE/Kq0Do81mHoW HArlAPtL5g7naJNtUK8YKzEIaX234zU= X-Google-Smtp-Source: AMsMyM6tbv+YFzHyjszXyqj0saRV+gxV1yRfBeysTnZ+b1CEJnqLPW6yPhfI7pQHvXWSznkdumvfvA== X-Received: by 2002:a17:907:8a23:b0:78d:a24e:a9aa with SMTP id sc35-20020a1709078a2300b0078da24ea9aamr5152391ejc.404.1665923305365; Sun, 16 Oct 2022 05:28:25 -0700 (PDT) Received: from localhost.localdomain (dynamic-089-014-006-139.89.14.pool.telefonica.de. [89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:25 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow , Bin Meng Subject: [PATCH v3 1/9] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two Date: Sun, 16 Oct 2022 14:27:29 +0200 Message-Id: <20221016122737.93755-2-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" According to the JEDEC standard the device length is communicated to an OS as an exponent (power of two). Signed-off-by: Bernhard Beschow Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 8 ++++++-- hw/block/pflash_cfi02.c | 5 +++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 0cbc2fb4cb..9c235bf66e 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -690,7 +690,7 @@ static const MemoryRegionOps pflash_cfi01_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl) +static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl, Error **errp) { uint64_t blocks_per_device, sector_len_per_device, device_len; int num_devices; @@ -708,6 +708,10 @@ static void pflash_cfi01_fill_cfi_table(PFlashCFI01 *pfl) sector_len_per_device = pfl->sector_len / num_devices; } device_len = sector_len_per_device * blocks_per_device; + if (!is_power_of_2(device_len)) { + error_setg(errp, "Device size must be a power of two."); + return; + } /* Hardcoded CFI table */ /* Standard "QRY" string */ @@ -865,7 +869,7 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) */ pfl->cmd = 0x00; pfl->status = 0x80; /* WSM ready */ - pflash_cfi01_fill_cfi_table(pfl); + pflash_cfi01_fill_cfi_table(pfl, errp); } static void pflash_cfi01_system_reset(DeviceState *dev) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 2a99b286b0..ff2fe154c1 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -880,6 +880,11 @@ static void pflash_cfi02_realize(DeviceState *dev, Error **errp) return; } + if (!is_power_of_2(pfl->chip_len)) { + error_setg(errp, "Device size must be a power of two."); + return; + } + memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), &pflash_cfi02_ops, pfl, pfl->name, pfl->chip_len, errp); From patchwork Sun Oct 16 12:27:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1690381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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[89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:26 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow Subject: [PATCH v3 2/9] hw/{arm,ppc}: Resolve unreachable code Date: Sun, 16 Oct 2022 14:27:30 +0200 Message-Id: <20221016122737.93755-3-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" pflash_cfi01_register() always returns with a non-NULL pointer (otherwise it would crash internally). Therefore, the bodies of the if-statements are unreachable. Signed-off-by: Bernhard Beschow --- hw/arm/gumstix.c | 18 ++++++------------ hw/arm/mainstone.c | 13 +++++-------- hw/arm/omap_sx1.c | 22 ++++++++-------------- hw/arm/versatilepb.c | 6 ++---- hw/arm/z2.c | 9 +++------ hw/ppc/sam460ex.c | 12 ++++-------- 6 files changed, 28 insertions(+), 52 deletions(-) diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 3a4bc332c4..1296628ed9 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -65,12 +65,9 @@ static void connex_init(MachineState *machine) exit(1); } - if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 2, 0, 0, 0, 0, 0)) { - error_report("Error registering flash memory"); - exit(1); - } + pflash_cfi01_register(0x00000000, "connext.rom", connex_rom, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 2, 0, 0, 0, 0, 0); /* Interrupt line of NIC is connected to GPIO line 36 */ smc91c111_init(&nd_table[0], 0x04000300, @@ -95,12 +92,9 @@ static void verdex_init(MachineState *machine) exit(1); } - if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 2, 0, 0, 0, 0, 0)) { - error_report("Error registering flash memory"); - exit(1); - } + pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 2, 0, 0, 0, 0, 0); /* Interrupt line of NIC is connected to GPIO line 99 */ smc91c111_init(&nd_table[0], 0x04000300, diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 8454b65458..40f708f2d3 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -130,14 +130,11 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, /* There are two 32MiB flash devices on the board */ for (i = 0; i < 2; i ++) { dinfo = drive_get(IF_PFLASH, 0, i); - if (!pflash_cfi01_register(mainstone_flash_base[i], - i ? "mainstone.flash1" : "mainstone.flash0", - MAINSTONE_FLASH, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 4, 0, 0, 0, 0, 0)) { - error_report("Error registering flash memory"); - exit(1); - } + pflash_cfi01_register(mainstone_flash_base[i], + i ? "mainstone.flash1" : "mainstone.flash0", + MAINSTONE_FLASH, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 4, 0, 0, 0, 0, 0); } mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS, diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 57829b3744..820652265b 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -153,13 +153,10 @@ static void sx1_init(MachineState *machine, const int version) fl_idx = 0; if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { - if (!pflash_cfi01_register(OMAP_CS0_BASE, - "omap_sx1.flash0-1", flash_size, - blk_by_legacy_dinfo(dinfo), - sector_size, 4, 0, 0, 0, 0, 0)) { - fprintf(stderr, "qemu: Error registering flash memory %d.\n", - fl_idx); - } + pflash_cfi01_register(OMAP_CS0_BASE, + "omap_sx1.flash0-1", flash_size, + blk_by_legacy_dinfo(dinfo), + sector_size, 4, 0, 0, 0, 0, 0); fl_idx++; } @@ -175,13 +172,10 @@ static void sx1_init(MachineState *machine, const int version) memory_region_add_subregion(address_space, OMAP_CS1_BASE + flash1_size, &cs[1]); - if (!pflash_cfi01_register(OMAP_CS1_BASE, - "omap_sx1.flash1-1", flash1_size, - blk_by_legacy_dinfo(dinfo), - sector_size, 4, 0, 0, 0, 0, 0)) { - fprintf(stderr, "qemu: Error registering flash memory %d.\n", - fl_idx); - } + pflash_cfi01_register(OMAP_CS1_BASE, + "omap_sx1.flash1-1", flash1_size, + blk_by_legacy_dinfo(dinfo), + sector_size, 4, 0, 0, 0, 0, 0); fl_idx++; } else { memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index ecc1f6cf74..43172d72ea 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -385,13 +385,11 @@ static void versatile_init(MachineState *machine, int board_id) /* 0x34000000 NOR Flash */ dinfo = drive_get(IF_PFLASH, 0, 0); - if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", + pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", VERSATILE_FLASH_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, VERSATILE_FLASH_SECT_SIZE, - 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { - fprintf(stderr, "qemu: Error registering flash memory.\n"); - } + 4, 0x0089, 0x0018, 0x0000, 0x0, 0); versatile_binfo.ram_size = machine->ram_size; versatile_binfo.board_id = board_id; diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 9c1e876207..082ccc557e 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -311,12 +311,9 @@ static void z2_init(MachineState *machine) mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type); dinfo = drive_get(IF_PFLASH, 0, 0); - if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 4, 0, 0, 0, 0, 0)) { - error_report("Error registering flash memory"); - exit(1); - } + pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 4, 0, 0, 0, 0, 0); /* setup keypad */ pxa27x_register_keypad(mpu->kp, map, 0x100); diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 850bb3b817..8089dd015b 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -111,14 +111,10 @@ static int sam460ex_load_uboot(void) DriveInfo *dinfo; dinfo = drive_get(IF_PFLASH, 0, 0); - if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), - "sam460ex.flash", FLASH_SIZE, - dinfo ? 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[89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:28 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow Subject: [PATCH v3 3/9] hw/block/pflash_cfi01: Attach memory region in boards Date: Sun, 16 Oct 2022 14:27:31 +0200 Message-Id: <20221016122737.93755-4-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" pflash_cfi01_register() had a parameter which was only passed to sysbus_mmio_map() but not used otherwise. Pulling out sysbus_mmio_map() resolves that parameter and concentrates the memory region setup in board code. Furthermore, it allows attaching cfi01 devices relative to some parent bus rather than to the global "sysbus". While at it, replace sysbus_mmio_map() with non-sysbus equivalents. Signed-off-by: Bernhard Beschow --- hw/arm/collie.c | 20 +++++++++++++------- hw/arm/gumstix.c | 18 ++++++++++++------ hw/arm/mainstone.c | 16 ++++++++++------ hw/arm/omap_sx1.c | 19 +++++++++++-------- hw/arm/versatilepb.c | 12 +++++++----- hw/arm/z2.c | 9 ++++++--- hw/block/pflash_cfi01.c | 4 +--- hw/microblaze/petalogix_ml605_mmu.c | 16 ++++++++++------ hw/microblaze/petalogix_s3adsp1800_mmu.c | 10 ++++++---- hw/mips/malta.c | 4 ++-- hw/ppc/sam460ex.c | 15 +++++++++------ hw/ppc/virtex_ml507.c | 5 ++++- include/hw/block/flash.h | 3 +-- 13 files changed, 92 insertions(+), 59 deletions(-) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 8df31e2793..25fb5f657b 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -37,8 +37,10 @@ static struct arm_boot_info collie_binfo = { static void collie_init(MachineState *machine) { DriveInfo *dinfo; + PFlashCFI01 *pfl; MachineClass *mc = MACHINE_GET_CLASS(machine); CollieMachineState *cms = COLLIE_MACHINE(machine); + MemoryRegion *system_memory = get_system_memory(); if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -49,17 +51,21 @@ static void collie_init(MachineState *machine) cms->sa1110 = sa1110_init(machine->cpu_type); - memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram); + memory_region_add_subregion(system_memory, SA_SDCS0, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + pfl = pflash_cfi01_register("collie.fl1", 0x02000000, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + memory_region_add_subregion(system_memory, SA_CS0, + pflash_cfi01_get_memory(pfl)); dinfo = drive_get(IF_PFLASH, 0, 1); - pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + pfl = pflash_cfi01_register("collie.fl2", 0x02000000, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + memory_region_add_subregion(system_memory, SA_CS1, + pflash_cfi01_get_memory(pfl)); sysbus_create_simple("scoop", 0x40800000, NULL); diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 1296628ed9..d6c997ad8e 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -51,6 +51,7 @@ static void connex_init(MachineState *machine) { PXA2xxState *cpu; DriveInfo *dinfo; + PFlashCFI01 *pfl; MemoryRegion *address_space_mem = get_system_memory(); uint32_t connex_rom = 0x01000000; @@ -65,9 +66,11 @@ static void connex_init(MachineState *machine) exit(1); } - pflash_cfi01_register(0x00000000, "connext.rom", connex_rom, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 2, 0, 0, 0, 0, 0); + pfl = pflash_cfi01_register("connext.rom", connex_rom, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 2, 0, 0, 0, 0, 0); + memory_region_add_subregion(address_space_mem, 0x00000000, + pflash_cfi01_get_memory(pfl)); /* Interrupt line of NIC is connected to GPIO line 36 */ smc91c111_init(&nd_table[0], 0x04000300, @@ -78,6 +81,7 @@ static void verdex_init(MachineState *machine) { PXA2xxState *cpu; DriveInfo *dinfo; + PFlashCFI01 *pfl; MemoryRegion *address_space_mem = get_system_memory(); uint32_t verdex_rom = 0x02000000; @@ -92,9 +96,11 @@ static void verdex_init(MachineState *machine) exit(1); } - pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 2, 0, 0, 0, 0, 0); + pfl = pflash_cfi01_register("verdex.rom", verdex_rom, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 2, 0, 0, 0, 0, 0); + memory_region_add_subregion(address_space_mem, 0x00000000, + pflash_cfi01_get_memory(pfl)); /* Interrupt line of NIC is connected to GPIO line 99 */ smc91c111_init(&nd_table[0], 0x04000300, diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 40f708f2d3..fbbaa4bf0c 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -116,7 +116,6 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; PXA2xxState *mpu; DeviceState *mst_irq; - DriveInfo *dinfo; int i; MemoryRegion *rom = g_new(MemoryRegion, 1); @@ -129,12 +128,17 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, /* There are two 32MiB flash devices on the board */ for (i = 0; i < 2; i ++) { + DriveInfo *dinfo; + PFlashCFI01 *fl; + dinfo = drive_get(IF_PFLASH, 0, i); - pflash_cfi01_register(mainstone_flash_base[i], - i ? "mainstone.flash1" : "mainstone.flash0", - MAINSTONE_FLASH, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 4, 0, 0, 0, 0, 0); + fl = pflash_cfi01_register(i ? "mainstone.flash1" : "mainstone.flash0", + MAINSTONE_FLASH, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 4, 0, 0, 0, 0, 0); + memory_region_add_subregion(address_space_mem, + mainstone_flash_base[i], + pflash_cfi01_get_memory(fl)); } mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS, diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 820652265b..ce06455252 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -112,6 +112,7 @@ static void sx1_init(MachineState *machine, const int version) static uint32_t cs2val = 0x00001139; static uint32_t cs3val = 0x00001139; DriveInfo *dinfo; + PFlashCFI01 *pfl; int fl_idx; uint32_t flash_size = flash0_size; @@ -153,10 +154,11 @@ static void sx1_init(MachineState *machine, const int version) fl_idx = 0; if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { - pflash_cfi01_register(OMAP_CS0_BASE, - "omap_sx1.flash0-1", flash_size, - blk_by_legacy_dinfo(dinfo), - sector_size, 4, 0, 0, 0, 0, 0); + pfl = pflash_cfi01_register("omap_sx1.flash0-1", flash_size, + blk_by_legacy_dinfo(dinfo), + sector_size, 4, 0, 0, 0, 0, 0); + memory_region_add_subregion(address_space, OMAP_CS0_BASE, + pflash_cfi01_get_memory(pfl)); fl_idx++; } @@ -172,10 +174,11 @@ static void sx1_init(MachineState *machine, const int version) memory_region_add_subregion(address_space, OMAP_CS1_BASE + flash1_size, &cs[1]); - pflash_cfi01_register(OMAP_CS1_BASE, - "omap_sx1.flash1-1", flash1_size, - blk_by_legacy_dinfo(dinfo), - sector_size, 4, 0, 0, 0, 0, 0); + pfl = pflash_cfi01_register("omap_sx1.flash1-1", flash1_size, + blk_by_legacy_dinfo(dinfo), + sector_size, 4, 0, 0, 0, 0, 0); + memory_region_add_subregion(address_space, OMAP_CS1_BASE, + pflash_cfi01_get_memory(pfl)); fl_idx++; } else { memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 43172d72ea..6ab85e304a 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -196,6 +196,7 @@ static void versatile_init(MachineState *machine, int board_id) int n; int done_smc = 0; DriveInfo *dinfo; + PFlashCFI01 *pfl; if (machine->ram_size > 0x10000000) { /* Device starting at address 0x10000000, @@ -385,11 +386,12 @@ static void versatile_init(MachineState *machine, int board_id) /* 0x34000000 NOR Flash */ dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", - VERSATILE_FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - VERSATILE_FLASH_SECT_SIZE, - 4, 0x0089, 0x0018, 0x0000, 0x0, 0); + pfl = pflash_cfi01_register("versatile.flash", VERSATILE_FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + VERSATILE_FLASH_SECT_SIZE, + 4, 0x0089, 0x0018, 0x0000, 0x0, 0); + memory_region_add_subregion(sysmem, VERSATILE_FLASH_ADDR, + pflash_cfi01_get_memory(pfl)); versatile_binfo.ram_size = machine->ram_size; versatile_binfo.board_id = board_id; diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 082ccc557e..79005cd171 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -303,6 +303,7 @@ static void z2_init(MachineState *machine) uint32_t sector_len = 0x10000; PXA2xxState *mpu; DriveInfo *dinfo; + PFlashCFI01 *pfl; void *z2_lcd; I2CBus *bus; DeviceState *wm; @@ -311,9 +312,11 @@ static void z2_init(MachineState *machine) mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 4, 0, 0, 0, 0, 0); + pfl = pflash_cfi01_register("z2.flash0", Z2_FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 4, 0, 0, 0, 0, 0); + memory_region_add_subregion(address_space_mem, Z2_FLASH_BASE, + pflash_cfi01_get_memory(pfl)); /* setup keypad */ pxa27x_register_keypad(mpu->kp, map, 0x100); diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 9c235bf66e..25d70dc3c0 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -957,8 +957,7 @@ static void pflash_cfi01_register_types(void) type_init(pflash_cfi01_register_types) -PFlashCFI01 *pflash_cfi01_register(hwaddr base, - const char *name, +PFlashCFI01 *pflash_cfi01_register(const char *name, hwaddr size, BlockBackend *blk, uint32_t sector_len, @@ -984,7 +983,6 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base, qdev_prop_set_string(dev, "name", name); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); return PFLASH_CFI01(dev); } diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index a24fadddca..14450ad372 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -76,6 +76,7 @@ petalogix_ml605_init(MachineState *machine) MicroBlazeCPU *cpu; SysBusDevice *busdev; DriveInfo *dinfo; + PFlashCFI01 *pfl; int i; MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); MemoryRegion *phys_ram = g_new(MemoryRegion, 1); @@ -103,12 +104,15 @@ petalogix_ml605_init(MachineState *machine) memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); - /* 5th parameter 2 means bank-width - * 10th paremeter 0 means little-endian */ - pflash_cfi01_register(FLASH_BASEADDR, "petalogix_ml605.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0); - + /* + * 4th parameter 2 means bank-width + * 9th paremeter 0 means little-endian + */ + pfl = pflash_cfi01_register("petalogix_ml605.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0); + memory_region_add_subregion(address_space_mem, FLASH_BASEADDR, + pflash_cfi01_get_memory(pfl)); dev = qdev_new("xlnx.xps-intc"); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 9d959d1ad8..a7eae72e02 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -62,6 +62,7 @@ petalogix_s3adsp1800_init(MachineState *machine) DeviceState *dev; MicroBlazeCPU *cpu; DriveInfo *dinfo; + PFlashCFI01 *pfl; int i; hwaddr ddr_base = MEMORY_BASEADDR; MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); @@ -84,10 +85,11 @@ petalogix_s3adsp1800_init(MachineState *machine) memory_region_add_subregion(sysmem, ddr_base, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(FLASH_BASEADDR, - "petalogix_s3adsp1800.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + pfl = pflash_cfi01_register("petalogix_s3adsp1800.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + memory_region_add_subregion(sysmem, FLASH_BASEADDR, + pflash_cfi01_get_memory(pfl)); dev = qdev_new("xlnx.xps-intc"); qdev_prop_set_uint32(dev, "kind-of-intr", diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 0e932988e0..20407bd998 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1286,12 +1286,12 @@ void mips_malta_init(MachineState *machine) /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); - fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", - FLASH_SIZE, + fl = pflash_cfi01_register("mips_malta.bios", FLASH_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 65536, 4, 0x0000, 0x0000, 0x0000, 0x0000, be); bios = pflash_cfi01_get_memory(fl); + memory_region_add_subregion(system_memory, FLASH_ADDRESS, bios); fl_idx++; if (kernel_filename) { ram_low_size = MIN(ram_size, 256 * MiB); diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 8089dd015b..6f4f9c7c4a 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -88,7 +88,7 @@ struct boot_info { uint32_t entry; }; -static int sam460ex_load_uboot(void) +static int sam460ex_load_uboot(MemoryRegion *address_space_mem) { /* * This first creates 1MiB of flash memory mapped at the end of @@ -109,12 +109,15 @@ static int sam460ex_load_uboot(void) */ DriveInfo *dinfo; + PFlashCFI01 *pfl; dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), - "sam460ex.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + pfl = pflash_cfi01_register("sam460ex.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + memory_region_add_subregion(address_space_mem, + FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), + pflash_cfi01_get_memory(pfl)); if (!dinfo) { /*error_report("No flash image given with the 'pflash' parameter," @@ -448,7 +451,7 @@ static void sam460ex_init(MachineState *machine) /* Load U-Boot image. */ if (!machine->kernel_filename) { - success = sam460ex_load_uboot(); + success = sam460ex_load_uboot(address_space_mem); if (success < 0) { error_report("could not load firmware"); exit(1); diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 493ea0c19f..c98f1b2ab3 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -210,6 +210,7 @@ static void virtex_init(MachineState *machine) CPUPPCState *env; hwaddr ram_base = 0; DriveInfo *dinfo; + PFlashCFI01 *pfl; qemu_irq irq[32], cpu_irq; int kernel_size; int i; @@ -229,9 +230,11 @@ static void virtex_init(MachineState *machine) memory_region_add_subregion(address_space_mem, ram_base, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, + pfl = pflash_cfi01_register("virtex.flash", FLASH_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + memory_region_add_subregion(address_space_mem, PFLASH_BASEADDR, + pflash_cfi01_get_memory(pfl)); cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT); dev = qdev_new("xlnx.xps-intc"); diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 86d8363bb0..5f9ba18de1 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -12,8 +12,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI01, PFLASH_CFI01) -PFlashCFI01 *pflash_cfi01_register(hwaddr base, - const char *name, +PFlashCFI01 *pflash_cfi01_register(const char *name, hwaddr size, BlockBackend *blk, uint32_t sector_len, From patchwork Sun Oct 16 12:27:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1690383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=HWrzsp3w; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Mr07w1Ccyz23jp for ; Sun, 16 Oct 2022 23:39:56 +1100 (AEDT) Received: from localhost ([::1]:53726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ok2vq-0002bi-17 for incoming@patchwork.ozlabs.org; Sun, 16 Oct 2022 08:39:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ok2kt-0002VL-Ev; Sun, 16 Oct 2022 08:28:35 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]:35808) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ok2kr-0000Qr-DI; Sun, 16 Oct 2022 08:28:35 -0400 Received: by mail-ej1-x631.google.com with SMTP id k2so19445432ejr.2; Sun, 16 Oct 2022 05:28:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cSCL1Ge340MOLsJbNs8WRE5yUKjbTgFBMKoLfI3Ami8=; b=HWrzsp3wBj2P5rbLGfZPG68FUfQ9ptwqP+IBUJ2oK45cySWrbpAvgSFQ5/CbhtkELi j7ZSQK7wEQXx7C9vxSuEjizZnmgdMWHHBE/ylUSaDjQLM1qOGYxR0ScphcZVBs41CWme GcSydz0H41i8pPhVvvGIUcTtrwj3JMUKe1KU5iTAu0PiX3WASbbjo2VmNEDC5mAHKaIk pff6lQvMgbR05Xg4iP/LoGXLxNzj4DW0VHD+rMIWRyCtDeW53kNQaMOipiWdBfkirJy7 ckHg6ZtI5HUuRGifD//PzArnydgTAi/tWySS4iCc3rNC4ZOfatIy1rDn+oGEJH9PFhLQ SrPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cSCL1Ge340MOLsJbNs8WRE5yUKjbTgFBMKoLfI3Ami8=; b=bXD1j+4fvfDMWY/IlgxU4FyQWizJ3qeJLA/xASi8Zgg+m9esDKDi9Nbk4XeCOH4IO3 Wqr2ZnfdUw2ODeAYfZ/bw2zi/pqeB7RqvKWemXv2g0K8mBLncqPPqifUAhLOQ+3sgaCz pZLjLJ6ErCaTMemMkpwKCZEk18nXizFZFvj18eEx+P0twcceoTUmtvSzWIo32XHD+8l8 M/tZJgA9CG9O7JSQhN2C05jXK3FWvpCZdsb+9SsN6IcTk7EzSx88dxF6GkhAzh4GYTra 8tns7j5RHiIhaq7IVtp5YCp0z9UUexRCYg19mrudyIU1mO5Yq1CuN0D0veGucLQy4ffp IPWg== X-Gm-Message-State: ACrzQf2Esv1JQxC/Zpy1cV/pLBIqD/RFJi/dd+csI1nCAY2B5NYtkYoU clFsUK1RhTWVD1RcVdcTKcY3Sper02U= X-Google-Smtp-Source: AMsMyM5IIFgZwm1w47fOgZta48zk/hdEDx81b46lOGCR/ws39a2IF/6ddP9lPiTykx7HbQHQ2Fiweg== X-Received: by 2002:a17:907:2672:b0:780:8bb5:25a3 with SMTP id ci18-20020a170907267200b007808bb525a3mr4968641ejc.281.1665923310314; Sun, 16 Oct 2022 05:28:30 -0700 (PDT) Received: from localhost.localdomain (dynamic-089-014-006-139.89.14.pool.telefonica.de. [89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:30 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow Subject: [PATCH v3 4/9] hw/block/pflash_cfi02: Attach memory region in boards Date: Sun, 16 Oct 2022 14:27:32 +0200 Message-Id: <20221016122737.93755-5-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" pflash_cfi02_register() had a parameter which was only passed to sysbus_mmio_map() but not used otherwise. Pulling out sysbus_mmio_map() resolves that parameter and concentrates the memory region setup in board code. Furthermore, it allows attaching cfi02 devices relative to some parent bus rather than to the global "sysbus". While at it, replace sysbus_mmio_map() with non-sysbus equivalents. Signed-off-by: Bernhard Beschow --- hw/arm/digic_boards.c | 16 ++++++++++------ hw/arm/musicpal.c | 15 +++++++++------ hw/arm/xilinx_zynq.c | 12 +++++++----- hw/block/pflash_cfi02.c | 9 ++++++--- hw/sh4/r2d.c | 11 +++++++---- include/hw/block/flash.h | 4 ++-- 6 files changed, 41 insertions(+), 26 deletions(-) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 4093af09cb..d3c5426cf9 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -116,12 +116,16 @@ static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr, #define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024) #define FLASH_K8P3215UQB_SECTOR_SIZE (64 * 1024) - pflash_cfi02_register(addr, "pflash", FLASH_K8P3215UQB_SIZE, - NULL, FLASH_K8P3215UQB_SECTOR_SIZE, - DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE, - 4, - 0x00EC, 0x007E, 0x0003, 0x0001, - 0x0555, 0x2aa, 0); + PFlashCFI02 *pfl; + + pfl = pflash_cfi02_register("pflash", FLASH_K8P3215UQB_SIZE, + NULL, FLASH_K8P3215UQB_SECTOR_SIZE, + DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE, + 4, + 0x00EC, 0x007E, 0x0003, 0x0001, + 0x0555, 0x2aa, 0); + memory_region_add_subregion(get_system_memory(), addr, + pflash_cfi02_get_memory(pfl)); digic_load_rom(s, addr, FLASH_K8P3215UQB_SIZE, filename); } diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index b65c020115..efad741f6d 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1261,6 +1261,7 @@ static void musicpal_init(MachineState *machine) /* Register flash */ dinfo = drive_get(IF_PFLASH, 0, 0); if (dinfo) { + PFlashCFI02 *pfl; BlockBackend *blk = blk_by_legacy_dinfo(dinfo); flash_size = blk_getlength(blk); @@ -1275,12 +1276,14 @@ static void musicpal_init(MachineState *machine) * 0xFF800000 (if there is 8 MB flash). So remap flash access if the * image is smaller than 32 MB. */ - pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, - "musicpal.flash", flash_size, - blk, 0x10000, - MP_FLASH_SIZE_MAX / flash_size, - 2, 0x00BF, 0x236D, 0x0000, 0x0000, - 0x5555, 0x2AAA, 0); + pfl = pflash_cfi02_register("musicpal.flash", flash_size, + blk, 0x10000, + MP_FLASH_SIZE_MAX / flash_size, + 2, 0x00BF, 0x236D, 0x0000, 0x0000, + 0x5555, 0x2AAA, 0); + memory_region_add_subregion(address_space_mem, + 0x100000000ULL - MP_FLASH_SIZE_MAX, + pflash_cfi02_get_memory(pfl)); } sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3190cc0b8d..a2abb1cf31 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -182,6 +182,7 @@ static void zynq_init(MachineState *machine) MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); DeviceState *dev, *slcr; SysBusDevice *busdev; + PFlashCFI02 *pfl; qemu_irq pic[64]; int n; @@ -218,11 +219,12 @@ static void zynq_init(MachineState *machine) DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); /* AMD */ - pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - FLASH_SECTOR_SIZE, 1, - 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, - 0); + pfl = pflash_cfi02_register("zynq.pflash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + FLASH_SECTOR_SIZE, 1, 1, 0x0066, 0x0022, 0x0000, + 0x0000, 0x0555, 0x2aa, 0); + memory_region_add_subregion(address_space_mem, 0xe2000000, + pflash_cfi02_get_memory(pfl)); /* Create the main clock source, and feed slcr with it */ zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index ff2fe154c1..60039e0d52 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -999,8 +999,7 @@ static void pflash_cfi02_register_types(void) type_init(pflash_cfi02_register_types) -PFlashCFI02 *pflash_cfi02_register(hwaddr base, - const char *name, +PFlashCFI02 *pflash_cfi02_register(const char *name, hwaddr size, BlockBackend *blk, uint32_t sector_len, @@ -1031,6 +1030,10 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, qdev_prop_set_string(dev, "name", name); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); return PFLASH_CFI02(dev); } + +MemoryRegion *pflash_cfi02_get_memory(PFlashCFI02 *fl) +{ + return sysbus_mmio_get_region(SYS_BUS_DEVICE(fl), 0); +} diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 39fc4f19d9..0af8f0e137 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -239,6 +239,7 @@ static void r2d_init(MachineState *machine) MemoryRegion *sdram = g_new(MemoryRegion, 1); qemu_irq *irq; DriveInfo *dinfo; + PFlashCFI02 *pfl; int i; DeviceState *dev; SysBusDevice *busdev; @@ -302,10 +303,12 @@ static void r2d_init(MachineState *machine) * addressable in words of 16bit. */ dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200, - 0x555, 0x2aa, 0); + pfl = pflash_cfi02_register("r2d.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200, + 0x555, 0x2aa, 0); + memory_region_add_subregion(get_system_memory(), 0x0, + pflash_cfi02_get_memory(pfl)); /* NIC: rtl8139 on-board, and 2 slots. */ for (i = 0; i < nb_nics; i++) diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 5f9ba18de1..52d6bcd56a 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -30,8 +30,7 @@ void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo); OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02) -PFlashCFI02 *pflash_cfi02_register(hwaddr base, - const char *name, +PFlashCFI02 *pflash_cfi02_register(const char *name, hwaddr size, BlockBackend *blk, uint32_t sector_len, @@ -42,6 +41,7 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, uint16_t unlock_addr0, uint16_t unlock_addr1, int be); +MemoryRegion *pflash_cfi02_get_memory(PFlashCFI02 *fl); /* nand.c */ DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id); From patchwork Sun Oct 16 12:27:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1690378 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=JylHANz/; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Mr0142fRNz23jn for ; Sun, 16 Oct 2022 23:33:58 +1100 (AEDT) Received: from localhost ([::1]:41860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ok2q3-0004uY-Cb for incoming@patchwork.ozlabs.org; Sun, 16 Oct 2022 08:33:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ok2ku-0002Xv-6N; Sun, 16 Oct 2022 08:28:36 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]:44762) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ok2ks-0000Re-Hy; Sun, 16 Oct 2022 08:28:35 -0400 Received: by mail-ej1-x636.google.com with SMTP id w18so19390617ejq.11; Sun, 16 Oct 2022 05:28:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WtEIJKc0Za2w7LkNpc+XYB5b7FTyMz3UDgQ3c6Pamy8=; b=JylHANz/NxFLncYjM07BEOn7wfjnHJsCvG6Z9+YXTf//6Bcu4sQ8GD0JvkGj1pRzQy 3549MQ0vvYXbVQEK8B2dOt3EVW1ctMer5/O2uLeHy+gwhRrOlilD9fV13527U6BPreFM 1KWTm3+muUIaP6m91G7wJWz4chfmCEdVgwVhtf4idHwdlbFeTDzcrhQRIl8qPee1TDK8 jykoNy5ZLHk7YhwMw00vGVvSOx6ZnKJjyG2AhNs1ZCVNioXN2pNyp/dFI2oge9Brasbf gE763LCtKJIW+xirjDPNbKw+wt8bt+T/J40W+WG23qjX8QHUMjFjbEMIeMe1e5BHCnLy bS6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WtEIJKc0Za2w7LkNpc+XYB5b7FTyMz3UDgQ3c6Pamy8=; b=TkhJKa+yoXMZGA5TQsl2ipH/3nqsscJlvKxN8D0mzxc+VWkP5XVY7nxbf4oXzEsLHM T8hrOANf7ACsEKFQlf19jrt6udlqUXmHKbFxzayy9+35OimMH5vymGwz4KviJ43ddK97 ULepFzEsJo76IjNYQoyLFUedt4huDo7Q4J3//LnnnDjK3TfXpe5JCRQD5IhCFSEIr2Cf ZzmB6D6wZX0v+O/rdrEGd0o936IFPZXhPPJ2KKuh6O4rSkFHhua6MvKC4/VBSR1kQjBo NPwj2A/51k69s13dwOCvCI9VxxLlM05zCjktHfgyVG1923cPxmE/XcG26UQeSn1CmnEF UhqA== X-Gm-Message-State: ACrzQf29OVSkjGoVYQJ+B6nJFu2yKHcw9ZaQnyugaTtLDf+DfvZYqCo7 dNXorycD1niR9eRcJfYtrHR+73YOUDc= X-Google-Smtp-Source: AMsMyM5mjiYtiPaalalX9SXXy3rGb/FHwZ0sVE5tSulgVloy5fuk2F0BTzmWAnr044Cy1+cdIrUQjg== X-Received: by 2002:a17:907:7f0b:b0:78d:c16e:e5fc with SMTP id qf11-20020a1709077f0b00b0078dc16ee5fcmr5130415ejc.713.1665923311797; Sun, 16 Oct 2022 05:28:31 -0700 (PDT) Received: from localhost.localdomain (dynamic-089-014-006-139.89.14.pool.telefonica.de. [89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:31 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow , Bin Meng Subject: [PATCH v3 5/9] hw/sd/sdhci-internal: Unexport ESDHC defines Date: Sun, 16 Oct 2022 14:27:33 +0200 Message-Id: <20221016122737.93755-6-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=shentey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" These defines aren't used outside of sdhci.c, so can be defined there. Signed-off-by: Bernhard Beschow Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-internal.h | 20 -------------------- hw/sd/sdhci.c | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index e8c753d6d1..964570f8e8 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -288,26 +288,6 @@ enum { extern const VMStateDescription sdhci_vmstate; - -#define ESDHC_MIX_CTRL 0x48 - -#define ESDHC_VENDOR_SPEC 0xc0 -#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8) - -#define ESDHC_DLL_CTRL 0x60 - -#define ESDHC_TUNING_CTRL 0xcc -#define ESDHC_TUNE_CTRL_STATUS 0x68 -#define ESDHC_WTMK_LVL 0x44 - -/* Undocumented register used by guests working around erratum ERR004536 */ -#define ESDHC_UNDOCUMENTED_REG27 0x6c - -#define ESDHC_CTRL_4BITBUS (0x1 << 1) -#define ESDHC_CTRL_8BITBUS (0x2 << 1) - -#define ESDHC_PRNSTS_SDSTB (1 << 3) - /* * Default SD/MMC host controller features information, which will be * presented in CAPABILITIES register of generic SD host controller at reset. diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 0e5e988927..6da5e2c781 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1577,6 +1577,25 @@ static const TypeInfo sdhci_bus_info = { /* --- qdev i.MX eSDHC --- */ +#define ESDHC_MIX_CTRL 0x48 + +#define ESDHC_VENDOR_SPEC 0xc0 +#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8) + +#define ESDHC_DLL_CTRL 0x60 + +#define ESDHC_TUNING_CTRL 0xcc +#define ESDHC_TUNE_CTRL_STATUS 0x68 +#define ESDHC_WTMK_LVL 0x44 + +/* Undocumented register used by guests working around erratum ERR004536 */ +#define ESDHC_UNDOCUMENTED_REG27 0x6c + +#define ESDHC_CTRL_4BITBUS (0x1 << 1) +#define ESDHC_CTRL_8BITBUS (0x2 << 1) + +#define ESDHC_PRNSTS_SDSTB (1 << 3) + static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) { SDHCIState *s = SYSBUS_SDHCI(opaque); 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[89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:32 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow , Bin Meng Subject: [PATCH v3 6/9] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_* Date: Sun, 16 Oct 2022 14:27:34 +0200 Message-Id: <20221016122737.93755-7-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=shentey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The device model's functions start with "usdhc_", so rename the defines accordingly for consistency. Signed-off-by: Bernhard Beschow Reviewed-by: Bin Meng --- hw/sd/sdhci.c | 66 +++++++++++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 6da5e2c781..306070c872 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1577,24 +1577,24 @@ static const TypeInfo sdhci_bus_info = { /* --- qdev i.MX eSDHC --- */ -#define ESDHC_MIX_CTRL 0x48 +#define USDHC_MIX_CTRL 0x48 -#define ESDHC_VENDOR_SPEC 0xc0 -#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8) +#define USDHC_VENDOR_SPEC 0xc0 +#define USDHC_IMX_FRC_SDCLK_ON (1 << 8) -#define ESDHC_DLL_CTRL 0x60 +#define USDHC_DLL_CTRL 0x60 -#define ESDHC_TUNING_CTRL 0xcc -#define ESDHC_TUNE_CTRL_STATUS 0x68 -#define ESDHC_WTMK_LVL 0x44 +#define USDHC_TUNING_CTRL 0xcc +#define USDHC_TUNE_CTRL_STATUS 0x68 +#define USDHC_WTMK_LVL 0x44 /* Undocumented register used by guests working around erratum ERR004536 */ -#define ESDHC_UNDOCUMENTED_REG27 0x6c +#define USDHC_UNDOCUMENTED_REG27 0x6c -#define ESDHC_CTRL_4BITBUS (0x1 << 1) -#define ESDHC_CTRL_8BITBUS (0x2 << 1) +#define USDHC_CTRL_4BITBUS (0x1 << 1) +#define USDHC_CTRL_8BITBUS (0x2 << 1) -#define ESDHC_PRNSTS_SDSTB (1 << 3) +#define USDHC_PRNSTS_SDSTB (1 << 3) static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) { @@ -1615,11 +1615,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); if (s->hostctl1 & SDHC_CTRL_8BITBUS) { - hostctl1 |= ESDHC_CTRL_8BITBUS; + hostctl1 |= USDHC_CTRL_8BITBUS; } if (s->hostctl1 & SDHC_CTRL_4BITBUS) { - hostctl1 |= ESDHC_CTRL_4BITBUS; + hostctl1 |= USDHC_CTRL_4BITBUS; } ret = hostctl1; @@ -1630,21 +1630,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) case SDHC_PRNSTS: /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ - ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; + ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB; if (s->clkcon & SDHC_CLOCK_INT_STABLE) { - ret |= ESDHC_PRNSTS_SDSTB; + ret |= USDHC_PRNSTS_SDSTB; } break; - case ESDHC_VENDOR_SPEC: + case USDHC_VENDOR_SPEC: ret = s->vendor_spec; break; - case ESDHC_DLL_CTRL: - case ESDHC_TUNE_CTRL_STATUS: - case ESDHC_UNDOCUMENTED_REG27: - case ESDHC_TUNING_CTRL: - case ESDHC_MIX_CTRL: - case ESDHC_WTMK_LVL: + case USDHC_DLL_CTRL: + case USDHC_TUNE_CTRL_STATUS: + case USDHC_UNDOCUMENTED_REG27: + case USDHC_TUNING_CTRL: + case USDHC_MIX_CTRL: + case USDHC_WTMK_LVL: ret = 0; break; } @@ -1660,18 +1660,18 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) uint32_t value = (uint32_t)val; switch (offset) { - case ESDHC_DLL_CTRL: - case ESDHC_TUNE_CTRL_STATUS: - case ESDHC_UNDOCUMENTED_REG27: - case ESDHC_TUNING_CTRL: - case ESDHC_WTMK_LVL: + case USDHC_DLL_CTRL: + case USDHC_TUNE_CTRL_STATUS: + case USDHC_UNDOCUMENTED_REG27: + case USDHC_TUNING_CTRL: + case USDHC_WTMK_LVL: break; - case ESDHC_VENDOR_SPEC: + case USDHC_VENDOR_SPEC: s->vendor_spec = value; switch (s->vendor) { case SDHCI_VENDOR_IMX: - if (value & ESDHC_IMX_FRC_SDCLK_ON) { + if (value & USDHC_IMX_FRC_SDCLK_ON) { s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; } else { s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; @@ -1740,12 +1740,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) * Second, split "Data Transfer Width" from bits 2 and 1 in to * bits 5 and 1 */ - if (value & ESDHC_CTRL_8BITBUS) { + if (value & USDHC_CTRL_8BITBUS) { hostctl1 |= SDHC_CTRL_8BITBUS; } - if (value & ESDHC_CTRL_4BITBUS) { - hostctl1 |= ESDHC_CTRL_4BITBUS; + if (value & USDHC_CTRL_4BITBUS) { + hostctl1 |= USDHC_CTRL_4BITBUS; } /* @@ -1768,7 +1768,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) sdhci_write(opaque, offset, value, size); break; - case ESDHC_MIX_CTRL: + case USDHC_MIX_CTRL: /* * So, when SD/MMC stack in Linux tries to write to "Transfer * Mode Register", ESDHC i.MX quirk code will translate it From patchwork Sun Oct 16 12:27:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1690392 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=knMAhHk+; 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[89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:34 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow Subject: [PATCH v3 7/9] hw/ppc/e500: Implement pflash handling Date: Sun, 16 Oct 2022 14:27:35 +0200 Message-Id: <20221016122737.93755-8-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Allows e500 boards to have their root file system reside on flash using only builtin devices located in the eLBC memory region. Note that the flash memory area is only created when a -pflash argument is given, and that the size is determined by the given file. The idea is to put users into control. Signed-off-by: Bernhard Beschow --- docs/system/ppc/ppce500.rst | 16 ++++++++++ hw/ppc/Kconfig | 1 + hw/ppc/e500.c | 62 +++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst index ba6bcb7314..99d2c680d6 100644 --- a/docs/system/ppc/ppce500.rst +++ b/docs/system/ppc/ppce500.rst @@ -165,3 +165,19 @@ if “-device eTSEC” is given to QEMU: .. code-block:: bash -netdev tap,ifname=tap0,script=no,downscript=no,id=net0 -device eTSEC,netdev=net0 + +Root file system on flash drive +------------------------------- + +Rather than using a root file system on ram disk, it is possible to have it on +CFI flash. Given an ext2 image whose size must be a power of two, it can be used +as follows: + +.. code-block:: bash + + $ qemu-system-ppc{64|32} -M ppce500 -cpu e500mc -smp 4 -m 2G \ + -display none -serial stdio \ + -kernel vmlinux \ + -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \ + -append "rootwait root=/dev/mtdblock0" + diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 791fe78a50..769a1ead1c 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -126,6 +126,7 @@ config E500 select ETSEC select GPIO_MPC8XXX select OPENPIC + select PFLASH_CFI01 select PLATFORM_BUS select PPCE500_PCI select SERIAL diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 3e950ea3ba..23d2c3451a 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -23,8 +23,10 @@ #include "e500-ccsr.h" #include "net/net.h" #include "qemu/config-file.h" +#include "hw/block/flash.h" #include "hw/char/serial.h" #include "hw/pci/pci.h" +#include "sysemu/block-backend-io.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -267,6 +269,31 @@ static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) } } +static void create_devtree_flash(SysBusDevice *sbdev, + PlatformDevtreeData *data) +{ + g_autofree char *name = NULL; + uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev), + "num-blocks", + &error_fatal); + uint64_t sector_length = object_property_get_uint(OBJECT(sbdev), + "sector-length", + &error_fatal); + uint64_t bank_width = object_property_get_uint(OBJECT(sbdev), + "width", + &error_fatal); + hwaddr flashbase = 0; + hwaddr flashsize = num_blocks * sector_length; + void *fdt = data->fdt; + + name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 1, flashbase, 1, flashsize); + qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width); +} + static void platform_bus_create_devtree(PPCE500MachineState *pms, void *fdt, const char *mpic) { @@ -276,6 +303,8 @@ static void platform_bus_create_devtree(PPCE500MachineState *pms, uint64_t addr = pmc->platform_bus_base; uint64_t size = pmc->platform_bus_size; int irq_start = pmc->platform_bus_first_irq; + SysBusDevice *sbdev; + bool ambiguous; /* Create a /platform node that we can put all devices into */ @@ -302,6 +331,13 @@ static void platform_bus_create_devtree(PPCE500MachineState *pms, /* Loop through all dynamic sysbus devices and create nodes for them */ foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); + sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01, + &ambiguous)); + if (sbdev) { + assert(!ambiguous); + create_devtree_flash(sbdev, &data); + } + g_free(node); } @@ -856,6 +892,7 @@ void ppce500_init(MachineState *machine) unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; IrqLines *irqs; DeviceState *dev, *mpicdev; + DriveInfo *dinfo; CPUPPCState *firstenv = NULL; MemoryRegion *ccsr_addr_space; SysBusDevice *s; @@ -1024,6 +1061,31 @@ void ppce500_init(MachineState *machine) pmc->platform_bus_base, &pms->pbus_dev->mmio); + dinfo = drive_get(IF_PFLASH, 0, 0); + if (dinfo) { + BlockBackend *blk = blk_by_legacy_dinfo(dinfo); + BlockDriverState *bs = blk_bs(blk); + uint64_t size = bdrv_getlength(bs); + uint64_t mmio_size = pms->pbus_dev->mmio.size; + PFlashCFI01 *pfl; + + if (!is_power_of_2(size)) { + error_report("Size of pflash file must be a power of two."); + exit(1); + } + + if (size > mmio_size) { + error_report("Size of pflash file must not be bigger than %" PRIu64 + " bytes.", mmio_size); + exit(1); + } + + pfl = pflash_cfi01_register("e500.flash", size, blk, 64 * KiB, 2, + 0x89, 0x18, 0x0000, 0x0, 1); + memory_region_add_subregion(&pms->pbus_dev->mmio, 0, + pflash_cfi01_get_memory(pfl)); + } + /* * Smart firmware defaults ahead! * From patchwork Sun Oct 16 12:27:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1690384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=NfJsutzC; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Mr09S3gcYz23kK for ; Sun, 16 Oct 2022 23:41:16 +1100 (AEDT) Received: from localhost ([::1]:37344 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ok2x8-0004DZ-C7 for incoming@patchwork.ozlabs.org; Sun, 16 Oct 2022 08:41:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ok2ky-0002hZ-UB; Sun, 16 Oct 2022 08:28:42 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]:34646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ok2kw-0000Ov-FO; Sun, 16 Oct 2022 08:28:40 -0400 Received: by mail-ej1-x62d.google.com with SMTP id ot12so19485188ejb.1; Sun, 16 Oct 2022 05:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YjMwr8cgXdmnl7qao2/HnRISq2gNWnT6j/SN7k814vg=; b=NfJsutzCcawqSgy6sp9sx4BncHauOevGyLJN6PppYmIg/Cy4NJ/uXZL6eRxcdEyafd xa2Q22GhaGyIBL9JN2GsEvv0bzfrxMLDA3PIwNIe758HCOY/t7iscO6hMEvGLtoim9y9 L8e71qgTP7oiE4jc/aaZJcVczf4mKp+YVkiXKc7Y2yOmgfig5O1eYv+19WtMKcQmoM7m T35fv6eKMaJHKOL7xQUFJqsNVJV7Xeatw2nF5rTiKi3tW8abt7NLfrfsvE9isNTQVspc KIBMO6t0uPTTxu8c1ukpTPEXZI2Fcvr9O7hMFX8NhiZMMKxf/mfQGl62ITvwf9P4JvB4 xG+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YjMwr8cgXdmnl7qao2/HnRISq2gNWnT6j/SN7k814vg=; b=pzbeefMRgzHUH0+RgO/tId4Jov0x7fWvcrTCGU3H25nGajLoVdxLKdEHzoEu6Wu3pE eopHuTTdirEUwj6FI7EjpaItRPyIdnBrAEQ4FjyIC95NUIRUNVJPbkf0Rh6Z4NZIY6NP egW2Kl7DQzJHn+6ruNCUQNi3dPDJFJ8gwMNK3XyvCRyBFwLtvpu5FvDrhWvLiFuAffac yJ88jbhfrDt8quTwAdVSP0KLtHQs08PCU/AKRIRDTV7eWJgmFmXCTvuReTaZtESb3HaI 6c7/Sqq3EULC6JwJCIuXx4lm9zBtTMq6ASLWMVjq6+nxzeqJPEgMdjgbYle/VrgU4miG sMkA== X-Gm-Message-State: ACrzQf2AbWAE+VYnw8nJWE/BBIcwSgwNfsGr31aCPokP6p1SWziJgDnl y8bly7HM+YAcONlUafUVXTyJEUSv5BY= X-Google-Smtp-Source: AMsMyM4k35PRrtcohrqbwuDVnRU2MW2epTJBwRLkFdfspbVa81Sv8sJubzy2wDq/ak/eP8b7xcfTow== X-Received: by 2002:a17:907:7e95:b0:78d:e9cf:82c7 with SMTP id qb21-20020a1709077e9500b0078de9cf82c7mr5111302ejc.724.1665923316278; Sun, 16 Oct 2022 05:28:36 -0700 (PDT) Received: from localhost.localdomain (dynamic-089-014-006-139.89.14.pool.telefonica.de. [89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:35 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow Subject: [PATCH v3 8/9] hw/sd/sdhci: Implement Freescale eSDHC device model Date: Sun, 16 Oct 2022 14:27:36 +0200 Message-Id: <20221016122737.93755-9-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Will allow e500 boards to access SD cards using just their own devices. Signed-off-by: Bernhard Beschow --- hw/sd/sdhci.c | 120 +++++++++++++++++++++++++++++++++++++++++- include/hw/sd/sdhci.h | 3 ++ 2 files changed, 122 insertions(+), 1 deletion(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 306070c872..8d8ad9ff24 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1369,6 +1369,7 @@ void sdhci_initfn(SDHCIState *s) s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); s->io_ops = &sdhci_mmio_ops; + s->io_registers_map_size = SDHC_REGISTERS_MAP_SIZE; } void sdhci_uninitfn(SDHCIState *s) @@ -1392,7 +1393,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp) s->fifo_buffer = g_malloc0(s->buf_maxsz); memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", - SDHC_REGISTERS_MAP_SIZE); + s->io_registers_map_size); } void sdhci_common_unrealize(SDHCIState *s) @@ -1575,6 +1576,122 @@ static const TypeInfo sdhci_bus_info = { .class_init = sdhci_bus_class_init, }; +/* --- qdev Freescale eSDHC --- */ + +/* Watermark Level Register */ +#define ESDHC_WML 0x44 + +/* Control Register for DMA transfer */ +#define ESDHC_DMA_SYSCTL 0x40c + +#define ESDHC_REGISTERS_MAP_SIZE 0x410 + +static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned size) +{ + uint64_t ret; + + switch (offset) { + case SDHC_SYSAD: + case SDHC_BLKSIZE: + case SDHC_ARGUMENT: + case SDHC_TRNMOD: + case SDHC_RSPREG0: + case SDHC_RSPREG1: + case SDHC_RSPREG2: + case SDHC_RSPREG3: + case SDHC_BDATA: + case SDHC_PRNSTS: + case SDHC_HOSTCTL: + case SDHC_CLKCON: + case SDHC_NORINTSTS: + case SDHC_NORINTSTSEN: + case SDHC_NORINTSIGEN: + case SDHC_ACMD12ERRSTS: + case SDHC_CAPAB: + case SDHC_SLOT_INT_STATUS: + ret = sdhci_read(opaque, offset, size); + break; + + case ESDHC_WML: + case ESDHC_DMA_SYSCTL: + ret = 0; + qemu_log_mask(LOG_UNIMP, "ESDHC rd @0x%02" HWADDR_PRIx + " not implemented\n", offset); + break; + + default: + ret = 0; + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd @0x%02" HWADDR_PRIx + " unknown offset\n", offset); + break; + } + + return ret; +} + +static void esdhci_write(void *opaque, hwaddr offset, uint64_t val, + unsigned size) +{ + switch (offset) { + case SDHC_SYSAD: + case SDHC_BLKSIZE: + case SDHC_ARGUMENT: + case SDHC_TRNMOD: + case SDHC_BDATA: + case SDHC_HOSTCTL: + case SDHC_CLKCON: + case SDHC_NORINTSTS: + case SDHC_NORINTSTSEN: + case SDHC_NORINTSIGEN: + case SDHC_FEAER: + sdhci_write(opaque, offset, val, size); + break; + + case ESDHC_WML: + case ESDHC_DMA_SYSCTL: + qemu_log_mask(LOG_UNIMP, "ESDHC wr @0x%02" HWADDR_PRIx " <- 0x%08lx " + "not implemented\n", offset, val); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr @0x%02" HWADDR_PRIx + " <- 0x%08lx unknown offset\n", offset, val); + break; + } +} + +static const MemoryRegionOps esdhc_mmio_ops = { + .read = esdhci_read, + .write = esdhci_write, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void esdhci_init(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + SDHCIState *s = SYSBUS_SDHCI(obj); + + s->io_ops = &esdhc_mmio_ops; + s->io_registers_map_size = ESDHC_REGISTERS_MAP_SIZE; + + /* + * Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + */ + qdev_prop_set_uint8(dev, "sd-spec-version", 2); +} + +static const TypeInfo esdhc_info = { + .name = TYPE_FSL_ESDHC, + .parent = TYPE_SYSBUS_SDHCI, + .instance_init = esdhci_init, +}; + /* --- qdev i.MX eSDHC --- */ #define USDHC_MIX_CTRL 0x48 @@ -1907,6 +2024,7 @@ static void sdhci_register_types(void) { type_register_static(&sdhci_sysbus_info); type_register_static(&sdhci_bus_info); + type_register_static(&esdhc_info); type_register_static(&imx_usdhc_info); type_register_static(&sdhci_s3c_info); } diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 01a64c5442..5b32e83eee 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -45,6 +45,7 @@ struct SDHCIState { AddressSpace *dma_as; MemoryRegion *dma_mr; const MemoryRegionOps *io_ops; + uint64_t io_registers_map_size; QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ QEMUTimer *transfer_timer; @@ -122,6 +123,8 @@ DECLARE_INSTANCE_CHECKER(SDHCIState, PCI_SDHCI, DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, TYPE_SYSBUS_SDHCI) +#define TYPE_FSL_ESDHC "fsl-esdhc" + #define TYPE_IMX_USDHC "imx-usdhc" #define TYPE_S3C_SDHCI "s3c-sdhci" From patchwork Sun Oct 16 12:27:37 2022 Content-Type: text/plain; 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[89.14.6.139]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm5504467edq.6.2022.10.16.05.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 05:28:37 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , qemu-arm@nongnu.org, Alistair Francis , Jan Kiszka , Magnus Damm , "Edgar E. Iglesias" , Kevin Wolf , qemu-block@nongnu.org, Bin Meng , Aurelien Jarno , qemu-ppc@nongnu.org, BALATON Zoltan , Yoshinori Sato , Antony Pavlov , Hanna Reitz , Bernhard Beschow Subject: [PATCH v3 9/9] hw/ppc/e500: Add Freescale eSDHC to e500plat Date: Sun, 16 Oct 2022 14:27:37 +0200 Message-Id: <20221016122737.93755-10-shentey@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221016122737.93755-1-shentey@gmail.com> References: <20221016122737.93755-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=shentey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Adds missing functionality to e500plat machine which increases the chance of given "real" firmware images to access SD cards. Signed-off-by: Bernhard Beschow --- docs/system/ppc/ppce500.rst | 12 ++++++++++++ hw/ppc/Kconfig | 1 + hw/ppc/e500.c | 35 ++++++++++++++++++++++++++++++++++- hw/ppc/e500.h | 1 + hw/ppc/e500plat.c | 1 + 5 files changed, 49 insertions(+), 1 deletion(-) diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst index 99d2c680d6..298ee9ee16 100644 --- a/docs/system/ppc/ppce500.rst +++ b/docs/system/ppc/ppce500.rst @@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices: * Power-off functionality via one GPIO pin * 1 Freescale MPC8xxx PCI host controller * VirtIO devices via PCI bus +* 1 Freescale Enhanced Secure Digital Host controller (eSDHC) * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC) Hardware configuration information @@ -181,3 +182,14 @@ as follows: -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \ -append "rootwait root=/dev/mtdblock0" +Alternatively, the root file system can also reside on an emulated SD card +whose size must again be a power of two: + +.. code-block:: bash + + $ qemu-system-ppc{64|32} -M ppce500 -cpu e500mc -smp 4 -m 2G \ + -display none -serial stdio \ + -kernel vmlinux \ + -device sd-card,drive=mydrive \ + -drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \ + -append "rootwait root=/dev/mmcblk0" diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index 769a1ead1c..6e31f568ba 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -129,6 +129,7 @@ config E500 select PFLASH_CFI01 select PLATFORM_BUS select PPCE500_PCI + select SDHCI select SERIAL select MPC_I2C select FDT_PPC diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 23d2c3451a..f43a21d8bb 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -48,6 +48,7 @@ #include "hw/net/fsl_etsec/etsec.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" +#include "hw/sd/sdhci.h" #define EPAPR_MAGIC (0x45504150) #define DTC_LOAD_PAD 0x1800000 @@ -66,11 +67,14 @@ #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL #define MPC8544_PCI_REGS_OFFSET 0x8000ULL #define MPC8544_PCI_REGS_SIZE 0x1000ULL +#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL +#define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL #define MPC8544_UTIL_OFFSET 0xe0000ULL #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL #define MPC8544_I2C_REGS_OFFSET 0x3000ULL #define MPC8XXX_GPIO_IRQ 47 #define MPC8544_I2C_IRQ 43 +#define MPC85XX_ESDHC_IRQ 72 #define RTC_REGS_OFFSET 0x68 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) @@ -203,6 +207,22 @@ static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, g_free(i2c); } +static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic) +{ + hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET; + hwaddr size = MPC85XX_ESDHC_REGS_SIZE; + int irq = MPC85XX_ESDHC_IRQ; + g_autofree char *name = NULL; + + name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0); + qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic); + qemu_fdt_setprop_cells(fdt, name, "bus-width", 4); + qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2); + qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size); + qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc"); +} typedef struct PlatformDevtreeData { void *fdt; @@ -553,6 +573,10 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms, dt_rtc_create(fdt, "i2c", "rtc"); + /* sdhc */ + if (pmc->has_esdhc) { + dt_sdhc_create(fdt, soc, mpic); + } gutil = g_strdup_printf("%s/global-utilities@%llx", soc, MPC8544_UTIL_OFFSET); @@ -982,7 +1006,8 @@ void ppce500_init(MachineState *machine) 0, qdev_get_gpio_in(mpicdev, 42), 399193, serial_hd(1), DEVICE_BIG_ENDIAN); } - /* I2C */ + + /* I2C */ dev = qdev_new("mpc-i2c"); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); @@ -992,6 +1017,14 @@ void ppce500_init(MachineState *machine) i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); + /* eSDHC */ + if (pmc->has_esdhc) { + dev = qdev_new(TYPE_FSL_ESDHC); + s = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ)); + } /* General Utility device */ dev = qdev_new("mpc8544-guts"); diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 68f754ce50..8c09ef92e4 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -27,6 +27,7 @@ struct PPCE500MachineClass { int mpic_version; bool has_mpc8xxx_gpio; + bool has_esdhc; hwaddr platform_bus_base; hwaddr platform_bus_size; int platform_bus_first_irq; diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 5bb1c603da..44bf874b0f 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -86,6 +86,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) pmc->fixup_devtree = e500plat_fixup_devtree; pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42; pmc->has_mpc8xxx_gpio = true; + pmc->has_esdhc = true; pmc->platform_bus_base = 0xf00000000ULL; pmc->platform_bus_size = 128 * MiB; pmc->platform_bus_first_irq = 5;