From patchwork Mon May 30 03:40:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 1636779 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=JfJvUldR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LBLsP0Rz3z9s5V for ; Mon, 30 May 2022 13:45:29 +1000 (AEST) Received: from localhost ([::1]:57588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvWLP-0002HR-1w for incoming@patchwork.ozlabs.org; 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X-IronPort-AV: E=McAfee;i="6400,9594,10362"; a="274974836" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974836" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2022 20:40:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993775" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 29 May 2022 20:40:50 -0700 From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 1/6] tests/acpi: allow SSDT changes Date: Mon, 30 May 2022 11:40:42 +0800 Message-Id: <20220530034047.730356-2-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..eb8bae1407 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/SSDT.dimmpxm", +"tests/data/acpi/q35/SSDT.dimmpxm", From patchwork Mon May 30 03:40:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 1636774 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=lT0K6jf/; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LBLnw3rpNz9s75 for ; Mon, 30 May 2022 13:42:26 +1000 (AEST) Received: from localhost ([::1]:49222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvWIR-000520-FS for incoming@patchwork.ozlabs.org; Sun, 29 May 2022 23:42:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40292) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvWH4-00051q-Rr for qemu-devel@nongnu.org; Sun, 29 May 2022 23:40:58 -0400 Received: from mga14.intel.com ([192.55.52.115]:36561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvWH1-0006wb-M1 for qemu-devel@nongnu.org; Sun, 29 May 2022 23:40:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653882055; x=1685418055; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LqufKj/Ys5thQqQmxH2lkTZN7JbW/gS9ajhvR+4AwM0=; b=lT0K6jf/IOW5FE01JNrJPZMr/GSETRJS4YxWizhDKF2CIOB/LwwFpaMJ UVNywFrWaFmDHKgwIzV0AqxuAY7v6yIFF8ikXkKBNYk/UPeoJETFLBEeC uU4wLSeHOlW0ZB1EWVOvffbhaxb2kYsotJ8KvvpI2+XeG7ijJkKpHq87T 8cekBAu0oJPlPe7oYk8wkGVSgh5HtjLppwd6iOUr9I7qwySbB1FOqPXSJ vx/KU08ZHHSrJTfkKrTbgz3gM16qVrckUznCy/CZpKzFaWyzPzNYOom1S 78xEKAEMOt5XagwhM7q4J2GXapSbJpGSFBwlDauW7QyhcAOKo/0mDWm++ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10362"; a="274974839" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974839" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2022 20:40:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993788" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 29 May 2022 20:40:52 -0700 From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 2/6] acpi/ssdt: Fix aml_or() and aml_and() in if clause Date: Mon, 30 May 2022 11:40:43 +0800 Message-Id: <20220530034047.730356-3-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In If condition, using bitwise and/or, rather than logical and/or. The result change in AML code: If (((Local6 == Zero) | (Arg0 != Local0))) ==> If (((Local6 == Zero) || (Arg0 != Local0))) If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) ==> If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One))) Fixes: 90623ebf603 ("nvdimm acpi: check UUID") Fixes: 4568c948066 ("nvdimm acpi: save arg3 of _DSM method") Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu Reviewed-by: Igor Mammedov --- hw/acpi/nvdimm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 0d43da19ea..0ab247a870 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -1040,7 +1040,7 @@ static void nvdimm_build_common_dsm(Aml *dev, uuid_invalid = aml_lnot(aml_equal(uuid, expected_uuid)); - unsupport = aml_if(aml_or(unpatched, uuid_invalid, NULL)); + unsupport = aml_if(aml_lor(unpatched, uuid_invalid)); /* * function 0 is called to inquire what functions are supported by @@ -1072,10 +1072,9 @@ static void nvdimm_build_common_dsm(Aml *dev, * in the DSM Spec. */ pckg = aml_arg(3); - ifctx = aml_if(aml_and(aml_equal(aml_object_type(pckg), + ifctx = aml_if(aml_land(aml_equal(aml_object_type(pckg), aml_int(4 /* Package */)) /* It is a Package? */, - aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? */, - NULL)); + aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? */)); pckg_index = aml_local(2); pckg_buf = aml_local(3); From patchwork Mon May 30 03:40:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 1636775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=SpcnV8cw; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LBLnw4ffGz9sBB for ; Mon, 30 May 2022 13:42:27 +1000 (AEST) Received: from localhost ([::1]:49270 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvWIS-00054V-D1 for incoming@patchwork.ozlabs.org; Sun, 29 May 2022 23:42:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvWH5-000521-Md for qemu-devel@nongnu.org; Sun, 29 May 2022 23:40:59 -0400 Received: from mga14.intel.com ([192.55.52.115]:36558) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nvWH3-0006wX-Gw for qemu-devel@nongnu.org; Sun, 29 May 2022 23:40:59 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653882057; x=1685418057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mKqNvHjGeoxS+aXxDCIjDV9OBVOE1uvThYOFAHUogmo=; b=SpcnV8cwcm+MLdRBARl6UgHqSkvDve7DS+Vf42oMiB910Ki279neRBZ+ s8PyKOU3VdnC8S5fmiEeG5zRbt3jHU9i0de3hC+Zm7PvvMbAJVVkHo43z E7gjmHwWR8qh2BtOxr3Oi3usv0Y2xfbmeviYfhNXS5pQy0UZxDum8am/H BP5S7Vw9/c+9VHf+9qCS9O8pqDS6B0r3DFo11c+dzh7GlUVOsKvDb6CMh dqfuc/o12Zv5WCpHedX2b7rE1DXTJH4SeMOmn4TJ2zShlrasKt0F8HK14 bVv/Yue/NgVLCd3e47EdJbAOIpH72doAVduxuFI5UWTYHk4QoR65wPWgQ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10362"; a="274974840" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974840" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2022 20:40:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993796" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 29 May 2022 20:40:54 -0700 From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 3/6] acpi/nvdimm: NVDIMM _DSM Spec supports revision 2 Date: Mon, 30 May 2022 11:40:44 +0800 Message-Id: <20220530034047.730356-4-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Intel Optane PMem DSM Interface, Version 2.0 [1], is the up-to-date spec for NVDIMM _DSM definition, which supports revision_id == 2. Nevertheless, Rev.2 of NVDIMM _DSM has no functional change on those Label Data _DSM Functions, which are the only ones implemented for vNVDIMM. So, simple change to support this revision_id == 2 case. [1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- hw/acpi/nvdimm.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 0ab247a870..59b42afcf1 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -849,9 +849,13 @@ nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", in->revision, in->handle, in->function); - if (in->revision != 0x1 /* Currently we only support DSM Spec Rev1. */) { - nvdimm_debug("Revision 0x%x is not supported, expect 0x%x.\n", - in->revision, 0x1); + /* + * Current NVDIMM _DSM Spec supports Rev1 and Rev2 + * Intel® OptanePersistent Memory Module DSM Interface, Revision 2.0 + */ + if (in->revision != 0x1 && in->revision != 0x2) { + nvdimm_debug("Revision 0x%x is not supported, expect 0x1 or 0x2.\n", + in->revision); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr); goto exit; } From patchwork Mon May 30 03:40:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 1636777 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=jfPc4/Bu; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LBLnx5lRrz9sBF for ; Mon, 30 May 2022 13:42:29 +1000 (AEST) Received: from localhost ([::1]:49488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nvWIV-0005DD-ST for incoming@patchwork.ozlabs.org; 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X-IronPort-AV: E=McAfee;i="6400,9594,10362"; a="274974848" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974848" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2022 20:40:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993814" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 29 May 2022 20:40:56 -0700 From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 4/6] nvdimm: Implement ACPI NVDIMM Label Methods Date: Mon, 30 May 2022 11:40:45 +0800 Message-Id: <20220530034047.730356-5-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which depricates corresponding _DSM Functions defined by PMEM _DSM Interface spec [2]. In this implementation, we do 2 things 1. Generalize the QEMU<->ACPI BIOS NVDIMM interface, wrap it with ACPI method dispatch, _DSM is one of the branches. This also paves the way for adding other ACPI methods for NVDIMM. 2. Add _LS{I,R,W} method in each NVDIMM device in SSDT. ASL form of SSDT changes can be found in next test/qtest/bios-table-test commit message. [1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf [2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- hw/acpi/nvdimm.c | 424 +++++++++++++++++++++++++++++++--------- include/hw/mem/nvdimm.h | 6 + 2 files changed, 338 insertions(+), 92 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 59b42afcf1..50ee85866b 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -416,17 +416,22 @@ static void nvdimm_build_nfit(NVDIMMState *state, GArray *table_offsets, #define NVDIMM_DSM_MEMORY_SIZE 4096 -struct NvdimmDsmIn { +struct NvdimmMthdIn { uint32_t handle; + uint32_t method; + uint8_t args[4088]; +} QEMU_PACKED; +typedef struct NvdimmMthdIn NvdimmMthdIn; +struct NvdimmDsmIn { uint32_t revision; uint32_t function; /* the remaining size in the page is used by arg3. */ union { - uint8_t arg3[4084]; + uint8_t arg3[4080]; }; } QEMU_PACKED; typedef struct NvdimmDsmIn NvdimmDsmIn; -QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmIn) != NVDIMM_DSM_MEMORY_SIZE); +QEMU_BUILD_BUG_ON(sizeof(NvdimmMthdIn) != NVDIMM_DSM_MEMORY_SIZE); struct NvdimmDsmOut { /* the size of buffer filled by QEMU. */ @@ -470,7 +475,8 @@ struct NvdimmFuncGetLabelDataIn { } QEMU_PACKED; typedef struct NvdimmFuncGetLabelDataIn NvdimmFuncGetLabelDataIn; QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataIn) + - offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE); + offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, args) > + NVDIMM_DSM_MEMORY_SIZE); struct NvdimmFuncGetLabelDataOut { /* the size of buffer filled by QEMU. */ @@ -488,14 +494,16 @@ struct NvdimmFuncSetLabelDataIn { } QEMU_PACKED; typedef struct NvdimmFuncSetLabelDataIn NvdimmFuncSetLabelDataIn; QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncSetLabelDataIn) + - offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE); + offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, args) > + NVDIMM_DSM_MEMORY_SIZE); struct NvdimmFuncReadFITIn { uint32_t offset; /* the offset into FIT buffer. */ } QEMU_PACKED; typedef struct NvdimmFuncReadFITIn NvdimmFuncReadFITIn; QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITIn) + - offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE); + offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, args) > + NVDIMM_DSM_MEMORY_SIZE); struct NvdimmFuncReadFITOut { /* the size of buffer filled by QEMU. */ @@ -636,7 +644,8 @@ static uint32_t nvdimm_get_max_xfer_label_size(void) * the max data ACPI can write one time which is transferred by * 'Set Namespace Label Data' function. */ - max_set_size = dsm_memory_size - offsetof(NvdimmDsmIn, arg3) - + max_set_size = dsm_memory_size - offsetof(NvdimmMthdIn, args) - + offsetof(NvdimmDsmIn, arg3) - sizeof(NvdimmFuncSetLabelDataIn); return MIN(max_get_size, max_set_size); @@ -697,16 +706,15 @@ static uint32_t nvdimm_rw_label_data_check(NVDIMMDevice *nvdimm, /* * DSM Spec Rev1 4.5 Get Namespace Label Data (Function Index 5). */ -static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in, - hwaddr dsm_mem_addr) +static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, + NvdimmFuncGetLabelDataIn *get_label_data, + hwaddr dsm_mem_addr) { NVDIMMClass *nvc = NVDIMM_GET_CLASS(nvdimm); - NvdimmFuncGetLabelDataIn *get_label_data; NvdimmFuncGetLabelDataOut *get_label_data_out; uint32_t status; int size; - get_label_data = (NvdimmFuncGetLabelDataIn *)in->arg3; get_label_data->offset = le32_to_cpu(get_label_data->offset); get_label_data->length = le32_to_cpu(get_label_data->length); @@ -737,15 +745,13 @@ static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in, /* * DSM Spec Rev1 4.6 Set Namespace Label Data (Function Index 6). */ -static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in, +static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, + NvdimmFuncSetLabelDataIn *set_label_data, hwaddr dsm_mem_addr) { NVDIMMClass *nvc = NVDIMM_GET_CLASS(nvdimm); - NvdimmFuncSetLabelDataIn *set_label_data; uint32_t status; - set_label_data = (NvdimmFuncSetLabelDataIn *)in->arg3; - set_label_data->offset = le32_to_cpu(set_label_data->offset); set_label_data->length = le32_to_cpu(set_label_data->length); @@ -760,19 +766,21 @@ static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in, } assert(offsetof(NvdimmDsmIn, arg3) + sizeof(*set_label_data) + - set_label_data->length <= NVDIMM_DSM_MEMORY_SIZE); + set_label_data->length <= NVDIMM_DSM_MEMORY_SIZE - + offsetof(NvdimmMthdIn, args)); nvc->write_label_data(nvdimm, set_label_data->in_buf, set_label_data->length, set_label_data->offset); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_SUCCESS, dsm_mem_addr); } -static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr dsm_mem_addr) +static void nvdimm_dsm_device(uint32_t nv_handle, NvdimmDsmIn *dsm_in, + hwaddr dsm_mem_addr) { - NVDIMMDevice *nvdimm = nvdimm_get_device_by_handle(in->handle); + NVDIMMDevice *nvdimm = nvdimm_get_device_by_handle(nv_handle); /* See the comments in nvdimm_dsm_root(). */ - if (!in->function) { + if (!dsm_in->function) { uint32_t supported_func = 0; if (nvdimm && nvdimm->label_size) { @@ -794,7 +802,7 @@ static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr dsm_mem_addr) } /* Encode DSM function according to DSM Spec Rev1. */ - switch (in->function) { + switch (dsm_in->function) { case 4 /* Get Namespace Label Size */: if (nvdimm->label_size) { nvdimm_dsm_label_size(nvdimm, dsm_mem_addr); @@ -803,13 +811,17 @@ static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr dsm_mem_addr) break; case 5 /* Get Namespace Label Data */: if (nvdimm->label_size) { - nvdimm_dsm_get_label_data(nvdimm, in, dsm_mem_addr); + nvdimm_dsm_get_label_data(nvdimm, + (NvdimmFuncGetLabelDataIn *)dsm_in->arg3, + dsm_mem_addr); return; } break; case 0x6 /* Set Namespace Label Data */: if (nvdimm->label_size) { - nvdimm_dsm_set_label_data(nvdimm, in, dsm_mem_addr); + nvdimm_dsm_set_label_data(nvdimm, + (NvdimmFuncSetLabelDataIn *)dsm_in->arg3, + dsm_mem_addr); return; } break; @@ -819,67 +831,128 @@ static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr dsm_mem_addr) } static uint64_t -nvdimm_dsm_read(void *opaque, hwaddr addr, unsigned size) +nvdimm_method_read(void *opaque, hwaddr addr, unsigned size) { - nvdimm_debug("BUG: we never read _DSM IO Port.\n"); + nvdimm_debug("BUG: we never read NVDIMM Method IO Port.\n"); return 0; } static void -nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +nvdimm_dsm_handle(void *opaque, NvdimmMthdIn *method_in, hwaddr dsm_mem_addr) { NVDIMMState *state = opaque; - NvdimmDsmIn *in; - hwaddr dsm_mem_addr = val; + NvdimmDsmIn *dsm_in = (NvdimmDsmIn *)method_in->args; nvdimm_debug("dsm memory address 0x%" HWADDR_PRIx ".\n", dsm_mem_addr); - /* - * The DSM memory is mapped to guest address space so an evil guest - * can change its content while we are doing DSM emulation. Avoid - * this by copying DSM memory to QEMU local memory. - */ - in = g_new(NvdimmDsmIn, 1); - cpu_physical_memory_read(dsm_mem_addr, in, sizeof(*in)); - - in->revision = le32_to_cpu(in->revision); - in->function = le32_to_cpu(in->function); - in->handle = le32_to_cpu(in->handle); - - nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", in->revision, - in->handle, in->function); + dsm_in->revision = le32_to_cpu(dsm_in->revision); + dsm_in->function = le32_to_cpu(dsm_in->function); + nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", + dsm_in->revision, method_in->handle, dsm_in->function); /* * Current NVDIMM _DSM Spec supports Rev1 and Rev2 * Intel® OptanePersistent Memory Module DSM Interface, Revision 2.0 */ - if (in->revision != 0x1 && in->revision != 0x2) { + if (dsm_in->revision != 0x1 && dsm_in->revision != 0x2) { nvdimm_debug("Revision 0x%x is not supported, expect 0x1 or 0x2.\n", - in->revision); + dsm_in->revision); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr); - goto exit; + return; } - if (in->handle == NVDIMM_QEMU_RSVD_HANDLE_ROOT) { - nvdimm_dsm_handle_reserved_root_method(state, in, dsm_mem_addr); - goto exit; + if (method_in->handle == NVDIMM_QEMU_RSVD_HANDLE_ROOT) { + nvdimm_dsm_handle_reserved_root_method(state, dsm_in, dsm_mem_addr); + return; } /* Handle 0 is reserved for NVDIMM Root Device. */ - if (!in->handle) { - nvdimm_dsm_root(in, dsm_mem_addr); - goto exit; + if (!method_in->handle) { + nvdimm_dsm_root(dsm_in, dsm_mem_addr); + return; } - nvdimm_dsm_device(in, dsm_mem_addr); + nvdimm_dsm_device(method_in->handle, dsm_in, dsm_mem_addr); +} -exit: - g_free(in); +static void nvdimm_lsi_handle(uint32_t nv_handle, hwaddr dsm_mem_addr) +{ + NVDIMMDevice *nvdimm = nvdimm_get_device_by_handle(nv_handle); + + if (nvdimm->label_size) { + nvdimm_dsm_label_size(nvdimm, dsm_mem_addr); + } + + return; +} + +static void nvdimm_lsr_handle(uint32_t nv_handle, + void *data, + hwaddr dsm_mem_addr) +{ + NVDIMMDevice *nvdimm = nvdimm_get_device_by_handle(nv_handle); + NvdimmFuncGetLabelDataIn *get_label_data = data; + + if (nvdimm->label_size) { + nvdimm_dsm_get_label_data(nvdimm, get_label_data, dsm_mem_addr); + } + return; +} + +static void nvdimm_lsw_handle(uint32_t nv_handle, + void *data, + hwaddr dsm_mem_addr) +{ + NVDIMMDevice *nvdimm = nvdimm_get_device_by_handle(nv_handle); + NvdimmFuncSetLabelDataIn *set_label_data = data; + + if (nvdimm->label_size) { + nvdimm_dsm_set_label_data(nvdimm, set_label_data, dsm_mem_addr); + } + return; +} + +static void +nvdimm_method_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + NvdimmMthdIn *method_in; + hwaddr dsm_mem_addr = val; + + /* + * The DSM memory is mapped to guest address space so an evil guest + * can change its content while we are doing DSM emulation. Avoid + * this by copying DSM memory to QEMU local memory. + */ + method_in = g_new(NvdimmMthdIn, 1); + cpu_physical_memory_read(dsm_mem_addr, method_in, sizeof(*method_in)); + + method_in->handle = le32_to_cpu(method_in->handle); + method_in->method = le32_to_cpu(method_in->method); + + switch (method_in->method) { + case NVDIMM_METHOD_DSM: + nvdimm_dsm_handle(opaque, method_in, dsm_mem_addr); + break; + case NVDIMM_METHOD_LSI: + nvdimm_lsi_handle(method_in->handle, dsm_mem_addr); + break; + case NVDIMM_METHOD_LSR: + nvdimm_lsr_handle(method_in->handle, method_in->args, dsm_mem_addr); + break; + case NVDIMM_METHOD_LSW: + nvdimm_lsw_handle(method_in->handle, method_in->args, dsm_mem_addr); + break; + default: + nvdimm_debug("%s: Unkown method 0x%x\n", __func__, method_in->method); + break; + } + + g_free(method_in); } -static const MemoryRegionOps nvdimm_dsm_ops = { - .read = nvdimm_dsm_read, - .write = nvdimm_dsm_write, +static const MemoryRegionOps nvdimm_method_ops = { + .read = nvdimm_method_read, + .write = nvdimm_method_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 4, @@ -899,12 +972,12 @@ void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, FWCfgState *fw_cfg, Object *owner) { state->dsm_io = dsm_io; - memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state, + memory_region_init_io(&state->io_mr, owner, &nvdimm_method_ops, state, "nvdimm-acpi-io", dsm_io.bit_width >> 3); memory_region_add_subregion(io, dsm_io.address, &state->io_mr); state->dsm_mem = g_array_new(false, true /* clear */, 1); - acpi_data_push(state->dsm_mem, sizeof(NvdimmDsmIn)); + acpi_data_push(state->dsm_mem, sizeof(NvdimmMthdIn)); fw_cfg_add_file(fw_cfg, NVDIMM_DSM_MEM_FILE, state->dsm_mem->data, state->dsm_mem->len); @@ -918,13 +991,22 @@ void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io, #define NVDIMM_DSM_IOPORT "NPIO" #define NVDIMM_DSM_NOTIFY "NTFI" +#define NVDIMM_DSM_METHOD "MTHD" #define NVDIMM_DSM_HANDLE "HDLE" #define NVDIMM_DSM_REVISION "REVS" #define NVDIMM_DSM_FUNCTION "FUNC" #define NVDIMM_DSM_ARG3 "FARG" -#define NVDIMM_DSM_OUT_BUF_SIZE "RLEN" -#define NVDIMM_DSM_OUT_BUF "ODAT" +#define NVDIMM_DSM_OFFSET "OFST" +#define NVDIMM_DSM_TRANS_LEN "TRSL" +#define NVDIMM_DSM_IN_BUFF "IDAT" + +#define NVDIMM_DSM_OUT_BUF_SIZE "RLEN" +#define NVDIMM_DSM_OUT_BUF "ODAT" +#define NVDIMM_DSM_OUT_STATUS "STUS" +#define NVDIMM_DSM_OUT_LSA_SIZE "SIZE" +#define NVDIMM_DSM_OUT_MAX_TRANS "MAXT" + #define NVDIMM_DSM_RFIT_STATUS "RSTA" @@ -938,7 +1020,6 @@ static void nvdimm_build_common_dsm(Aml *dev, Aml *pckg, *pckg_index, *pckg_buf, *field, *dsm_out_buf, *dsm_out_buf_size; Aml *whilectx, *offset; uint8_t byte_list[1]; - AmlRegionSpace rs; method = aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED); uuid = aml_arg(0); @@ -949,37 +1030,15 @@ static void nvdimm_build_common_dsm(Aml *dev, aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), dsm_mem)); - if (nvdimm_state->dsm_io.space_id == AML_AS_SYSTEM_IO) { - rs = AML_SYSTEM_IO; - } else { - rs = AML_SYSTEM_MEMORY; - } - - /* map DSM memory and IO into ACPI namespace. */ - aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, rs, - aml_int(nvdimm_state->dsm_io.address), - nvdimm_state->dsm_io.bit_width >> 3)); aml_append(method, aml_operation_region(NVDIMM_DSM_MEMORY, - AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmDsmIn))); - - /* - * DSM notifier: - * NVDIMM_DSM_NOTIFY: write the address of DSM memory and notify QEMU to - * emulate the access. - * - * It is the IO port so that accessing them will cause VM-exit, the - * control will be transferred to QEMU. - */ - field = aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK, - AML_PRESERVE); - aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY, - nvdimm_state->dsm_io.bit_width)); - aml_append(method, field); + AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmMthdIn))); /* * DSM input: * NVDIMM_DSM_HANDLE: store device's handle, it's zero if the _DSM call * happens on NVDIMM Root Device. + * NVDIMM_DSM_METHOD: ACPI method indicator, to distinguish _DSM and + * other ACPI methods. * NVDIMM_DSM_REVISION: store the Arg1 of _DSM call. * NVDIMM_DSM_FUNCTION: store the Arg2 of _DSM call. * NVDIMM_DSM_ARG3: store the Arg3 of _DSM call which is a Package @@ -991,13 +1050,16 @@ static void nvdimm_build_common_dsm(Aml *dev, field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, - sizeof(typeof_field(NvdimmDsmIn, handle)) * BITS_PER_BYTE)); + sizeof(typeof_field(NvdimmMthdIn, handle)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * BITS_PER_BYTE)); aml_append(field, aml_named_field(NVDIMM_DSM_REVISION, sizeof(typeof_field(NvdimmDsmIn, revision)) * BITS_PER_BYTE)); aml_append(field, aml_named_field(NVDIMM_DSM_FUNCTION, sizeof(typeof_field(NvdimmDsmIn, function)) * BITS_PER_BYTE)); aml_append(field, aml_named_field(NVDIMM_DSM_ARG3, - (sizeof(NvdimmDsmIn) - offsetof(NvdimmDsmIn, arg3)) * BITS_PER_BYTE)); + (sizeof(NvdimmMthdIn) - offsetof(NvdimmMthdIn, args) - + offsetof(NvdimmDsmIn, arg3)) * BITS_PER_BYTE)); aml_append(method, field); /* @@ -1065,6 +1127,7 @@ static void nvdimm_build_common_dsm(Aml *dev, * it reserves 0 for root device and is the handle for NVDIMM devices. * See the comments in nvdimm_slot_to_handle(). */ + aml_append(method, aml_store(aml_int(0), aml_name(NVDIMM_DSM_METHOD))); aml_append(method, aml_store(handle, aml_name(NVDIMM_DSM_HANDLE))); aml_append(method, aml_store(aml_arg(1), aml_name(NVDIMM_DSM_REVISION))); aml_append(method, aml_store(function, aml_name(NVDIMM_DSM_FUNCTION))); @@ -1250,6 +1313,7 @@ static void nvdimm_build_fit(Aml *dev) static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots) { uint32_t slot; + Aml *method, *pkg, *field; for (slot = 0; slot < ram_slots; slot++) { uint32_t handle = nvdimm_slot_to_handle(slot); @@ -1266,6 +1330,155 @@ static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots) * table NFIT or _FIT. */ aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle))); + aml_append(nvdimm_dev, aml_operation_region(NVDIMM_DSM_MEMORY, + AML_SYSTEM_MEMORY, aml_name(NVDIMM_ACPI_MEM_ADDR), + sizeof(NvdimmMthdIn))); + + /* ACPI 6.4: 6.5.10 NVDIMM Label Methods, _LS{I,R,W} */ + + /* Begin of _LSI Block */ + method = aml_method("_LSI", 0, AML_SERIALIZED); + /* _LSI Input field */ + field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, + sizeof(typeof_field(NvdimmMthdIn, handle)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * BITS_PER_BYTE)); + aml_append(method, field); + + /* _LSI Output field */ + field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, len)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_STATUS, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, + func_ret_status)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_LSA_SIZE, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, label_size)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_MAX_TRANS, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, max_xfer)) * + BITS_PER_BYTE)); + aml_append(method, field); + + aml_append(method, aml_store(aml_int(handle), + aml_name(NVDIMM_DSM_HANDLE))); + aml_append(method, aml_store(aml_int(0x100), + aml_name(NVDIMM_DSM_METHOD))); + aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), + aml_name(NVDIMM_DSM_NOTIFY))); + + pkg = aml_package(3); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_STATUS)); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_LSA_SIZE)); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_MAX_TRANS)); + + aml_append(method, aml_name_decl("RPKG", pkg)); + + aml_append(method, aml_return(aml_name("RPKG"))); + aml_append(nvdimm_dev, method); /* End of _LSI Block */ + + + /* Begin of _LSR Block */ + method = aml_method("_LSR", 2, AML_SERIALIZED); + + /* _LSR Input field */ + field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, + sizeof(typeof_field(NvdimmMthdIn, handle)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OFFSET, + sizeof(typeof_field(NvdimmFuncGetLabelDataIn, offset)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_TRANS_LEN, + sizeof(typeof_field(NvdimmFuncGetLabelDataIn, length)) * + BITS_PER_BYTE)); + aml_append(method, field); + + /* _LSR Output field */ + field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE, + sizeof(typeof_field(NvdimmFuncGetLabelDataOut, len)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_STATUS, + sizeof(typeof_field(NvdimmFuncGetLabelDataOut, + func_ret_status)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF, + (NVDIMM_DSM_MEMORY_SIZE - + offsetof(NvdimmFuncGetLabelDataOut, out_buf)) * + BITS_PER_BYTE)); + aml_append(method, field); + + aml_append(method, aml_store(aml_int(handle), + aml_name(NVDIMM_DSM_HANDLE))); + aml_append(method, aml_store(aml_int(0x101), + aml_name(NVDIMM_DSM_METHOD))); + aml_append(method, aml_store(aml_arg(0), aml_name(NVDIMM_DSM_OFFSET))); + aml_append(method, aml_store(aml_arg(1), + aml_name(NVDIMM_DSM_TRANS_LEN))); + aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), + aml_name(NVDIMM_DSM_NOTIFY))); + + aml_append(method, aml_store(aml_shiftleft(aml_arg(1), aml_int(3)), + aml_local(1))); + aml_append(method, aml_create_field(aml_name(NVDIMM_DSM_OUT_BUF), + aml_int(0), aml_local(1), "OBUF")); + + pkg = aml_package(2); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_STATUS)); + aml_append(pkg, aml_name("OBUF")); + aml_append(method, aml_name_decl("RPKG", pkg)); + + aml_append(method, aml_return(aml_name("RPKG"))); + aml_append(nvdimm_dev, method); /* End of _LSR Block */ + + /* Begin of _LSW Block */ + method = aml_method("_LSW", 3, AML_SERIALIZED); + /* _LSW Input field */ + field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, + sizeof(typeof_field(NvdimmMthdIn, handle)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OFFSET, + sizeof(typeof_field(NvdimmFuncSetLabelDataIn, offset)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_TRANS_LEN, + sizeof(typeof_field(NvdimmFuncSetLabelDataIn, length)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_IN_BUFF, 32640)); + aml_append(method, field); + + /* _LSW Output field */ + field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE, + sizeof(typeof_field(NvdimmDsmFuncNoPayloadOut, len)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_STATUS, + sizeof(typeof_field(NvdimmDsmFuncNoPayloadOut, + func_ret_status)) * BITS_PER_BYTE)); + aml_append(method, field); + + aml_append(method, aml_store(aml_int(handle), aml_name(NVDIMM_DSM_HANDLE))); + aml_append(method, aml_store(aml_int(0x102), aml_name(NVDIMM_DSM_METHOD))); + aml_append(method, aml_store(aml_arg(0), aml_name(NVDIMM_DSM_OFFSET))); + aml_append(method, aml_store(aml_arg(1), aml_name(NVDIMM_DSM_TRANS_LEN))); + aml_append(method, aml_store(aml_arg(2), aml_name(NVDIMM_DSM_IN_BUFF))); + aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), + aml_name(NVDIMM_DSM_NOTIFY))); + + aml_append(method, aml_return(aml_name(NVDIMM_DSM_OUT_STATUS))); + aml_append(nvdimm_dev, method); /* End of _LSW Block */ nvdimm_build_device_dsm(nvdimm_dev, handle); aml_append(root_dev, nvdimm_dev); @@ -1278,7 +1491,8 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, uint32_t ram_slots, const char *oem_id) { int mem_addr_offset; - Aml *ssdt, *sb_scope, *dev; + Aml *ssdt, *sb_scope, *dev, *field; + AmlRegionSpace rs; AcpiTable table = { .sig = "SSDT", .rev = 1, .oem_id = oem_id, .oem_table_id = "NVDIMM" }; @@ -1286,6 +1500,9 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, acpi_table_begin(&table, table_data); ssdt = init_aml_allocator(); + + mem_addr_offset = build_append_named_dword(table_data, + NVDIMM_ACPI_MEM_ADDR); sb_scope = aml_scope("\\_SB"); dev = aml_device("NVDR"); @@ -1303,6 +1520,31 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, */ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012"))); + if (nvdimm_state->dsm_io.space_id == AML_AS_SYSTEM_IO) { + rs = AML_SYSTEM_IO; + } else { + rs = AML_SYSTEM_MEMORY; + } + + /* map DSM memory and IO into ACPI namespace. */ + aml_append(dev, aml_operation_region(NVDIMM_DSM_IOPORT, rs, + aml_int(nvdimm_state->dsm_io.address), + nvdimm_state->dsm_io.bit_width >> 3)); + + /* + * DSM notifier: + * NVDIMM_DSM_NOTIFY: write the address of DSM memory and notify QEMU to + * emulate the access. + * + * It is the IO port so that accessing them will cause VM-exit, the + * control will be transferred to QEMU. + */ + field = aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY, + nvdimm_state->dsm_io.bit_width)); + aml_append(dev, field); + nvdimm_build_common_dsm(dev, nvdimm_state); /* 0 is reserved for root device. */ @@ -1316,12 +1558,10 @@ static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data, /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); - mem_addr_offset = build_append_named_dword(table_data, - NVDIMM_ACPI_MEM_ADDR); bios_linker_loader_alloc(linker, NVDIMM_DSM_MEM_FILE, nvdimm_state->dsm_mem, - sizeof(NvdimmDsmIn), false /* high memory */); + sizeof(NvdimmMthdIn), false /* high memory */); bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t), NVDIMM_DSM_MEM_FILE, 0); diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index cf8f59be44..0206b6125b 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -37,6 +37,12 @@ } \ } while (0) +/* NVDIMM ACPI Methods */ +#define NVDIMM_METHOD_DSM 0 +#define NVDIMM_METHOD_LSI 0x100 +#define NVDIMM_METHOD_LSR 0x101 +#define NVDIMM_METHOD_LSW 0x102 + /* * The minimum label data size is required by NVDIMM Namespace * specification, see the chapter 2 Namespaces: From patchwork Mon May 30 03:40:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 1636780 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=msUxdJPF; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 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xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 5/6] test/acpi/bios-tables-test: SSDT: update golden master binaries Date: Mon, 30 May 2022 11:40:46 +0800 Message-Id: <20220530034047.730356-6-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Diff in disassembled ASL files @@ -1,100 +1,103 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20190509 (64-bit version) * Copyright (c) 2000 - 2019 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/SSDT.dimmpxm, Wed May 25 11:02:18 2022 + * Disassembly of /tmp/aml-U0ONM1, Wed May 25 11:02:18 2022 * * Original Table Header: * Signature "SSDT" - * Length 0x000002DE (734) + * Length 0x00000725 (1829) * Revision 0x01 - * Checksum 0x46 + * Checksum 0xEA * OEM ID "BOCHS " * OEM Table ID "NVDIMM" * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) { + Name (MEMA, 0x07FFF000) Scope (\_SB) { Device (NVDR) { Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID + OperationRegion (NPIO, SystemIO, 0x0A18, 0x04) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + Method (NCAL, 5, Serialized) { Local6 = MEMA /* \MEMA */ - OperationRegion (NPIO, SystemIO, 0x0A18, 0x04) OperationRegion (NRAM, SystemMemory, Local6, 0x1000) - Field (NPIO, DWordAcc, NoLock, Preserve) - { - NTFI, 32 - } - Field (NRAM, DWordAcc, NoLock, Preserve) { HDLE, 32, + MTHD, 32, REVS, 32, FUNC, 32, - FARG, 32672 + FARG, 32640 } Field (NRAM, DWordAcc, NoLock, Preserve) { RLEN, 32, ODAT, 32736 } If ((Arg4 == Zero)) { Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") } ElseIf ((Arg4 == 0x00010000)) { Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") } Else { Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") } - If (((Local6 == Zero) | (Arg0 != Local0))) + If (((Local6 == Zero) || (Arg0 != Local0))) { If ((Arg2 == Zero)) { Return (Buffer (One) { 0x00 // . }) } Return (Buffer (One) { 0x01 // . }) } + MTHD = Zero HDLE = Arg4 REVS = Arg1 FUNC = Arg2 - If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One))) { Local2 = Arg3 [Zero] Local3 = DerefOf (Local2) FARG = Local3 } NTFI = Local6 Local1 = (RLEN - 0x04) If ((Local1 < 0x08)) { Local2 = Zero Name (TBUF, Buffer (One) { 0x00 // . }) Local7 = Buffer (Zero){} @@ -161,45 +164,304 @@ Else { If ((Local1 == Zero)) { Return (Local2) } Local3 += Local1 Concatenate (Local2, Local0, Local2) } } } Device (NV00) { Name (_ADR, One) // _ADR: Address + OperationRegion (NRAM, SystemMemory, MEMA, 0x1000) + Method (_LSI, 0, Serialized) // _LSI: Label Storage Information + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + SIZE, 32, + MAXT, 32 + } + + HDLE = One + MTHD = 0x0100 + NTFI = MEMA /* \MEMA */ + Name (RPKG, Package (0x03) + { + STUS, + SIZE, + MAXT + }) + Return (RPKG) /* \_SB_.NVDR.NV00._LSI.RPKG */ + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + ODAT, 32704 + } + + HDLE = One + MTHD = 0x0101 + OFST = Arg0 + TRSL = Arg1 + NTFI = MEMA /* \MEMA */ + Local1 = (Arg1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Name (RPKG, Package (0x02) + { + STUS, + OBUF + }) + Return (RPKG) /* \_SB_.NVDR.NV00._LSR.RPKG */ + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32, + IDAT, 32640 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32 + } + + HDLE = One + MTHD = 0x0102 + OFST = Arg0 + TRSL = Arg1 + IDAT = Arg2 + NTFI = MEMA /* \MEMA */ + Return (STUS) /* \_SB_.NVDR.NV00._LSW.STUS */ + } + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) } } Device (NV01) { Name (_ADR, 0x02) // _ADR: Address + OperationRegion (NRAM, SystemMemory, MEMA, 0x1000) + Method (_LSI, 0, Serialized) // _LSI: Label Storage Information + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + SIZE, 32, + MAXT, 32 + } + + HDLE = 0x02 + MTHD = 0x0100 + NTFI = MEMA /* \MEMA */ + Name (RPKG, Package (0x03) + { + STUS, + SIZE, + MAXT + }) + Return (RPKG) /* \_SB_.NVDR.NV01._LSI.RPKG */ + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + ODAT, 32704 + } + + HDLE = 0x02 + MTHD = 0x0101 + OFST = Arg0 + TRSL = Arg1 + NTFI = MEMA /* \MEMA */ + Local1 = (Arg1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Name (RPKG, Package (0x02) + { + STUS, + OBUF + }) + Return (RPKG) /* \_SB_.NVDR.NV01._LSR.RPKG */ + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32, + IDAT, 32640 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32 + } + + HDLE = 0x02 + MTHD = 0x0102 + OFST = Arg0 + TRSL = Arg1 + IDAT = Arg2 + NTFI = MEMA /* \MEMA */ + Return (STUS) /* \_SB_.NVDR.NV01._LSW.STUS */ + } + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) } } Device (NV02) { Name (_ADR, 0x03) // _ADR: Address + OperationRegion (NRAM, SystemMemory, MEMA, 0x1000) + Method (_LSI, 0, Serialized) // _LSI: Label Storage Information + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + SIZE, 32, + MAXT, 32 + } + + HDLE = 0x03 + MTHD = 0x0100 + NTFI = MEMA /* \MEMA */ + Name (RPKG, Package (0x03) + { + STUS, + SIZE, + MAXT + }) + Return (RPKG) /* \_SB_.NVDR.NV02._LSI.RPKG */ + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + ODAT, 32704 + } + + HDLE = 0x03 + MTHD = 0x0101 + OFST = Arg0 + TRSL = Arg1 + NTFI = MEMA /* \MEMA */ + Local1 = (Arg1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Name (RPKG, Package (0x02) + { + STUS, + OBUF + }) + Return (RPKG) /* \_SB_.NVDR.NV02._LSR.RPKG */ + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32, + IDAT, 32640 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32 + } + + HDLE = 0x03 + MTHD = 0x0102 + OFST = Arg0 + TRSL = Arg1 + IDAT = Arg2 + NTFI = MEMA /* \MEMA */ + Return (STUS) /* \_SB_.NVDR.NV02._LSW.STUS */ + } + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) } } } } - - Name (MEMA, 0x07FFF000) } Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- tests/data/acpi/pc/SSDT.dimmpxm | Bin 734 -> 1829 bytes tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 1829 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/pc/SSDT.dimmpxm b/tests/data/acpi/pc/SSDT.dimmpxm index ac55387d57e48adb99eb738a102308688a262fb8..672d51bc348366f667b1d3aeeec45dd06727fd5b 100644 GIT binary patch literal 1829 zcmc&!L1@!p6n<&Tnx&mIU14LQ#DizM9YpXTY16E6Ob z31Sy^5s`G{D0mmVdG+MUn}>mSFN%no_jh&JUFJ6M^8d-7?|<)m@B3bKT{5ml0hsTZ zQZ}y(#d%3l)!-cfG7IG_?yQ))bgCrKe%Ay*Vil4z{|jCxb-)8 z@3Olb#|kLm%Zn%Xdhe6josY`9*E4S&t2aT<)2~Le{MZ5C?Xn=mpVuvKvg_7i*Ilx_ zQMUy?A7<#n5I|yN899u1i7qPwT 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files to ignore */ -"tests/data/acpi/pc/SSDT.dimmpxm", -"tests/data/acpi/q35/SSDT.dimmpxm", From patchwork Mon May 30 03:40:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Hoo X-Patchwork-Id: 1636781 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=WZM8Ql1n; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org 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bh=HngbqauiXuP/VRSQc50sk+fwRp63LRe1ydbgVBKmJL4=; b=WZM8Ql1nEZG9zEoLqg0KlzegctXcvUL/eEhiGF7JbFHVlVmvO7LOoIK7 QDwu8Ju3hEQQC5VNZJUT38PYJVQ7nMaLTtFvggZK1/SubMw2+D19E7xgq 9RYEIq8jk5KP1XljXBSX/x1Y2y7S7JLaWyKinh6BTRKD8YB6wBZYPOJ8U WKaFvIQFsc++z5c2qHrny/rsbeO+Km/QcvnNTAQArlLoXuDR5m9rJucw1 2GahnSkT6ILsyJlxlDEkI15ZlgEFXla8VdbVQ7OMqxUW3Qb2AbwGwI6LR q9oCoTAtsKKOUKgSTgvitvw3LPAR8F1M2bGY8MWWTONxslepgZvWqbF7/ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10362"; a="274974865" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974865" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2022 20:41:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993841" Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 29 May 2022 20:41:01 -0700 From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 6/6] acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug() Date: Mon, 30 May 2022 11:40:47 +0800 Message-Id: <20220530034047.730356-7-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- hw/acpi/nvdimm.c | 38 ++++++++++++++++++-------------------- hw/acpi/trace-events | 14 ++++++++++++++ include/hw/mem/nvdimm.h | 8 -------- 3 files changed, 32 insertions(+), 28 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 50ee85866b..fc777990e6 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -35,6 +35,7 @@ #include "hw/nvram/fw_cfg.h" #include "hw/mem/nvdimm.h" #include "qemu/nvdimm-utils.h" +#include "trace.h" /* * define Byte Addressable Persistent Memory (PM) Region according to @@ -558,8 +559,8 @@ static void nvdimm_dsm_func_read_fit(NVDIMMState *state, NvdimmDsmIn *in, fit = fit_buf->fit; - nvdimm_debug("Read FIT: offset 0x%x FIT size 0x%x Dirty %s.\n", - read_fit->offset, fit->len, fit_buf->dirty ? "Yes" : "No"); + trace_acpi_nvdimm_read_fit(read_fit->offset, fit->len, + fit_buf->dirty ? "Yes" : "No"); if (read_fit->offset > fit->len) { func_ret_status = NVDIMM_DSM_RET_STATUS_INVALID; @@ -667,7 +668,7 @@ static void nvdimm_dsm_label_size(NVDIMMDevice *nvdimm, hwaddr dsm_mem_addr) label_size = nvdimm->label_size; mxfer = nvdimm_get_max_xfer_label_size(); - nvdimm_debug("label_size 0x%x, max_xfer 0x%x.\n", label_size, mxfer); + trace_acpi_nvdimm_label_info(label_size, mxfer); label_size_out.func_ret_status = cpu_to_le32(NVDIMM_DSM_RET_STATUS_SUCCESS); label_size_out.label_size = cpu_to_le32(label_size); @@ -683,20 +684,18 @@ static uint32_t nvdimm_rw_label_data_check(NVDIMMDevice *nvdimm, uint32_t ret = NVDIMM_DSM_RET_STATUS_INVALID; if (offset + length < offset) { - nvdimm_debug("offset 0x%x + length 0x%x is overflow.\n", offset, - length); + trace_acpi_nvdimm_label_overflow(offset, length); return ret; } if (nvdimm->label_size < offset + length) { - nvdimm_debug("position 0x%x is beyond label data (len = %" PRIx64 ").\n", - offset + length, nvdimm->label_size); + trace_acpi_nvdimm_label_oversize(offset + length, nvdimm->label_size); return ret; } if (length > nvdimm_get_max_xfer_label_size()) { - nvdimm_debug("length (0x%x) is larger than max_xfer (0x%x).\n", - length, nvdimm_get_max_xfer_label_size()); + trace_acpi_nvdimm_label_xfer_exceed(length, + nvdimm_get_max_xfer_label_size()); return ret; } @@ -718,8 +717,8 @@ static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, get_label_data->offset = le32_to_cpu(get_label_data->offset); get_label_data->length = le32_to_cpu(get_label_data->length); - nvdimm_debug("Read Label Data: offset 0x%x length 0x%x.\n", - get_label_data->offset, get_label_data->length); + trace_acpi_nvdimm_read_label(get_label_data->offset, + get_label_data->length); status = nvdimm_rw_label_data_check(nvdimm, get_label_data->offset, get_label_data->length); @@ -755,8 +754,8 @@ static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, set_label_data->offset = le32_to_cpu(set_label_data->offset); set_label_data->length = le32_to_cpu(set_label_data->length); - nvdimm_debug("Write Label Data: offset 0x%x length 0x%x.\n", - set_label_data->offset, set_label_data->length); + trace_acpi_nvdimm_write_label(set_label_data->offset, + set_label_data->length); status = nvdimm_rw_label_data_check(nvdimm, set_label_data->offset, set_label_data->length); @@ -833,7 +832,7 @@ static void nvdimm_dsm_device(uint32_t nv_handle, NvdimmDsmIn *dsm_in, static uint64_t nvdimm_method_read(void *opaque, hwaddr addr, unsigned size) { - nvdimm_debug("BUG: we never read NVDIMM Method IO Port.\n"); + trace_acpi_nvdimm_read_io_port(); return 0; } @@ -843,20 +842,19 @@ nvdimm_dsm_handle(void *opaque, NvdimmMthdIn *method_in, hwaddr dsm_mem_addr) NVDIMMState *state = opaque; NvdimmDsmIn *dsm_in = (NvdimmDsmIn *)method_in->args; - nvdimm_debug("dsm memory address 0x%" HWADDR_PRIx ".\n", dsm_mem_addr); + trace_acpi_nvdimm_dsm_mem_addr(dsm_mem_addr); dsm_in->revision = le32_to_cpu(dsm_in->revision); dsm_in->function = le32_to_cpu(dsm_in->function); - nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", - dsm_in->revision, method_in->handle, dsm_in->function); + trace_acpi_nvdimm_dsm_info(dsm_in->revision, + method_in->handle, dsm_in->function); /* * Current NVDIMM _DSM Spec supports Rev1 and Rev2 * Intel® OptanePersistent Memory Module DSM Interface, Revision 2.0 */ if (dsm_in->revision != 0x1 && dsm_in->revision != 0x2) { - nvdimm_debug("Revision 0x%x is not supported, expect 0x1 or 0x2.\n", - dsm_in->revision); + trace_acpi_nvdimm_invalid_revision(dsm_in->revision); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr); return; } @@ -943,7 +941,7 @@ nvdimm_method_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) nvdimm_lsw_handle(method_in->handle, method_in->args, dsm_mem_addr); break; default: - nvdimm_debug("%s: Unkown method 0x%x\n", __func__, method_in->method); + trace_acpi_nvdimm_invalid_method(method_in->method); break; } diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events index 2250126a22..db4c69009f 100644 --- a/hw/acpi/trace-events +++ b/hw/acpi/trace-events @@ -70,3 +70,17 @@ acpi_erst_reset_out(unsigned record_count) "record_count %u" acpi_erst_post_load(void *header, unsigned slot_size) "header: 0x%p slot_size %u" acpi_erst_class_init_in(void) acpi_erst_class_init_out(void) + +# nvdimm.c +acpi_nvdimm_read_fit(uint32_t offset, uint32_t len, const char *dirty) "Read FIT: offset 0x%" PRIx32 " FIT size 0x%" PRIx32 " Dirty %s" +acpi_nvdimm_label_info(uint32_t label_size, uint32_t mxfer) "label_size 0x%" PRIx32 ", max_xfer 0x%" PRIx32 +acpi_nvdimm_label_overflow(uint32_t offset, uint32_t length) "offset 0x%" PRIx32 " + length 0x%" PRIx32 " is overflow" +acpi_nvdimm_label_oversize(uint32_t pos, uint64_t size) "position 0x%" PRIx32 " is beyond label data (len = %" PRIu64 ")" +acpi_nvdimm_label_xfer_exceed(uint32_t length, uint32_t max_xfer) "length (0x%" PRIx32 ") is larger than max_xfer (0x%" PRIx32 ")" +acpi_nvdimm_read_label(uint32_t offset, uint32_t length) "Read Label Data: offset 0x%" PRIx32 " length 0x%" PRIx32 +acpi_nvdimm_write_label(uint32_t offset, uint32_t length) "Write Label Data: offset 0x%" PRIx32 " length 0x%" PRIx32 +acpi_nvdimm_read_io_port(void) "Alert: we never read NVDIMM Method IO Port" +acpi_nvdimm_dsm_mem_addr(uint64_t dsm_mem_addr) "dsm memory address 0x%" PRIx64 +acpi_nvdimm_dsm_info(uint32_t revision, uint32_t handle, uint32_t function) "Revision 0x%" PRIx32 " Handle 0x%" PRIx32 " Function 0x%" PRIx32 +acpi_nvdimm_invalid_revision(uint32_t revision) "Revision 0x%" PRIx32 " is not supported, expect 0x1 or 0x2" +acpi_nvdimm_invalid_method(uint32_t method) "Unkown method %" PRId32 diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 0206b6125b..c83e273829 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -29,14 +29,6 @@ #include "hw/acpi/aml-build.h" #include "qom/object.h" -#define NVDIMM_DEBUG 0 -#define nvdimm_debug(fmt, ...) \ - do { \ - if (NVDIMM_DEBUG) { \ - fprintf(stderr, "nvdimm: " fmt, ## __VA_ARGS__); \ - } \ - } while (0) - /* NVDIMM ACPI Methods */ #define NVDIMM_METHOD_DSM 0 #define NVDIMM_METHOD_LSI 0x100