From patchwork Tue May 10 11:29:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1629077 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=irq.a4lg.com header.i=@irq.a4lg.com header.a=rsa-sha256 header.s=2017s01 header.b=IPcM4zp8; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KyG6V4hc8z9sGF for ; Tue, 10 May 2022 21:29:54 +1000 (AEST) Received: from localhost ([::1]:41612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noO3s-0001Vk-FO for incoming@patchwork.ozlabs.org; Tue, 10 May 2022 07:29:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55330) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noO3N-0001PO-Mp; Tue, 10 May 2022 07:29:22 -0400 Received: from mail-sender.a4lg.com ([153.120.152.154]:53432 helo=mail-sender-0.a4lg.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noO3M-0005W4-6I; Tue, 10 May 2022 07:29:21 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 67378300089; Tue, 10 May 2022 11:29:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652182157; bh=k4cEuaC6bA4rdhfTVEofobxO31uBFWRb292qS9w0pLE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=IPcM4zp8Wnmsz3o7xF8/IPmvYe3ke57EBOt/Flh2jlRk4NgXC/aV5SwRmDoUK6Xt3 v3U64zxPI8k2bn6W/BPV/mMTTWIO6dVpYC/qXsGV5LjxUpK3ydkZIObYf+ZzaDz1mU yw7hqFxYx6efxqi5dN/sULZSWfplLygi/45erw7k= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang , Weiwei Li Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 1/2] target/riscv: Move Zhinx* extensions on ISA string Date: Tue, 10 May 2022 20:29:07 +0900 Message-Id: <7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=153.120.152.154; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This commit moves ISA string conversion for Zhinx and Zhinxmin extensions. Because extension category ordering of "H" is going to be after "V", their ordering is going to be valid (on canonical order). Signed-off-by: Tsukasa OI Acked-by: Alistair Francis --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..9f38e56316 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -999,8 +999,6 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) ISA_EDATA_ENTRY(zfh, ext_zfh), ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), ISA_EDATA_ENTRY(zfinx, ext_zfinx), - ISA_EDATA_ENTRY(zhinx, ext_zhinx), - ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), ISA_EDATA_ENTRY(zdinx, ext_zdinx), ISA_EDATA_ENTRY(zba, ext_zba), ISA_EDATA_ENTRY(zbb, ext_zbb), @@ -1021,6 +1019,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) ISA_EDATA_ENTRY(zkt, ext_zkt), ISA_EDATA_ENTRY(zve32f, ext_zve32f), ISA_EDATA_ENTRY(zve64f, ext_zve64f), + ISA_EDATA_ENTRY(zhinx, ext_zhinx), + ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), ISA_EDATA_ENTRY(svinval, ext_svinval), ISA_EDATA_ENTRY(svnapot, ext_svnapot), ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), From patchwork Tue May 10 11:29:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 1629081 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=irq.a4lg.com header.i=@irq.a4lg.com header.a=rsa-sha256 header.s=2017s01 header.b=K3fgDvng; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KyG972SGKz9sGF for ; Tue, 10 May 2022 21:32:11 +1000 (AEST) Received: from localhost ([::1]:49388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noO65-0006mT-6i for incoming@patchwork.ozlabs.org; Tue, 10 May 2022 07:32:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noO3U-0001dY-24; Tue, 10 May 2022 07:29:28 -0400 Received: from mail-sender-0.a4lg.com ([2401:2500:203:30b:4000:6bfe:4757:0]:47836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noO3S-0005Wf-Bk; Tue, 10 May 2022 07:29:27 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id EAC3C300089; Tue, 10 May 2022 11:29:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1652182163; bh=6ieKT6SMeR6ROD/gvppds4+LUmTz5zlH/XobTZVD7BA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=K3fgDvngT0t8Igu4WP+vNqnTqQSFaS8zShe6q3jg2MrWIDJEYlVbONjjiRlE6IouC 3mz0xySKhVbqXCNg8oXG/zAsujjh2wvnZia0q8RKUk0xT3cfIhQLkcBJgUJbvcHFCI NVEJmuExyXwgUfENJJRqvB70krr6H55/ouFyAazo= From: Tsukasa OI To: Tsukasa OI , Alistair Francis , Frank Chang , Weiwei Li Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/2] target/riscv: Add short-isa-string option Date: Tue, 10 May 2022 20:29:08 +0900 Message-Id: <7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Received-SPF: pass client-ip=2401:2500:203:30b:4000:6bfe:4757:0; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Because some operating systems don't correctly parse long ISA extension string, this commit adds short-isa-string boolean option to disable generating long ISA extension strings on Device Tree. For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or earlier) with FPU support caused a kernel panic. Operating Systems which short-isa-string might be helpful: 1. Linux (5.17 or earlier) 2. FreeBSD (at least 14.0-CURRENT) 3. OpenBSD (at least current development version) Signed-off-by: Tsukasa OI Acked-by: Alistair Francis --- target/riscv/cpu.c | 5 ++++- target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f38e56316..4db3dce25a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -879,6 +879,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), + + DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), DEFINE_PROP_END_OF_LIST(), }; @@ -1049,7 +1051,8 @@ char *riscv_isa_string(RISCVCPU *cpu) } } *p = '\0'; - riscv_isa_string_ext(cpu, &isa_str, maxlen); + if (!cpu->cfg.short_isa_string) + riscv_isa_string_ext(cpu, &isa_str, maxlen); return isa_str; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe6c9a2c92..f5ff7294c6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -425,6 +425,8 @@ struct RISCVCPUConfig { bool aia; bool debug; uint64_t resetvec; + + bool short_isa_string; }; typedef struct RISCVCPUConfig RISCVCPUConfig;