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[78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:45:53 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 1/7] hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration Date: Wed, 16 Feb 2022 23:45:13 +0100 Message-Id: <20220216224519.157233-2-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=shentey@gmail.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Based on commit e735b55a8c11dd455e31ccd4420e6c9485191d0c: piix_pci: eliminate PIIX3State::pci_irq_levels PIIX3State::pci_irq_levels are redundant which is already tracked by PCIBus layer. So eliminate them. The IRQ levels in the PCIBus layer are already preserved during migration. By reusing them and rather than having a redundant implementation the bug is avoided in the first place. Suggested-by: Peter Maydell Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/mips/gt64xxx_pci.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index c7480bd019..4cbd0911f5 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1006,14 +1006,11 @@ static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) } } -static int pci_irq_levels[4]; - static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; qemu_irq *pic = opaque; - - pci_irq_levels[irq_num] = level; + PCIBus *bus = pci_get_bus(piix4_dev); /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ @@ -1023,7 +1020,7 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) pic_level = 0; for (i = 0; i < 4; i++) { if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { - pic_level |= pci_irq_levels[i]; + pic_level |= pci_bus_get_irq_level(bus, i); } } qemu_set_irq(pic[pic_irq], pic_level); From patchwork Wed Feb 16 22:45:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1593951 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=o5l5HENx; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JzY6009Nqz9sFN for ; Thu, 17 Feb 2022 09:48:40 +1100 (AEDT) Received: from localhost ([::1]:33416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKT6D-0001tF-Rs for incoming@patchwork.ozlabs.org; Wed, 16 Feb 2022 17:48:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKT3f-0007aG-DZ for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:46:01 -0500 Received: from [2a00:1450:4864:20::62c] (port=38414 helo=mail-ej1-x62c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nKT3d-0003Rc-B3 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:45:59 -0500 Received: by mail-ej1-x62c.google.com with SMTP id k25so2584953ejp.5 for ; Wed, 16 Feb 2022 14:45:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6GvV2G4gMyq/5hU5hxpAas4ZwKkNIA0PxeXiCQrawKI=; b=o5l5HENx+MKQSW7RLhHPgl81ks6qOIH9HIUXHC/7lNVzQ7RhPVcUww43IZ/Hspuq0+ MJuOL0s5ERNR+dyE9MaK2bejFpUCockhMSr/kaKEPir81pO2UIlTj/Hweuh8LlkKn5Fm 5jO/dlyC9PFBgqka6/eEzDH1keFpAxHQ9ItczGSI4wZe5Gw0tMfDh5AVpamYmpLeTzn5 oOghssruqJTWNYBMRBIUZqqmcSJQMr8XBBAB7o8fbKlw1i+I86zJFf1pXEJogCZWqVaP sJmNtHWb3zAZ+5/EfwXBUXbONuhaCPuf9LF1alUR5gM/2rIH/BwnU9AkttHL0Octk5xM O8kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6GvV2G4gMyq/5hU5hxpAas4ZwKkNIA0PxeXiCQrawKI=; b=W188BL2RvHnJJfGbDYQQ6fHCdDYrIej7yD9sV+EzcCO9oXRxF3D3gnsYHZu2E56cUd 7fp9NHVm0KZ5/8O5aaDzx/tyThLfe5W1Ael/Sy+wk9TwwbPb24XnV+dRC1MMHGj8e06X nVkrriXwqJrlzarR92ii2D0LEhdzFrdVgwdsnNgwqYqiA0jlLNm4OWeeMw2709m1GNmj Fmr3epGm96J7WBIIHc3We9fW+McHrLm08MmYk3CIb3tFfXvG2iA/4MTe8oMn9h71I9st 3DuRuFmLkXnnXEY1dRNxPt2Q3+h5JgBLYw+VW42R+s0mgO+gU+EMgylw7Mctkei852jE LhEQ== X-Gm-Message-State: AOAM531307jIu30sVOsJQhEVyCjCDzv7vUf7kbRX3owi760sCF44NOnV B5Xa/40dFrwYCk7zL2OyvG/ZNAz1Cu0= X-Google-Smtp-Source: ABdhPJw/+10t3IFRt6NidLH4rlg7hcAxBI9O5n8yK+sgTAmC/5Q69AoKao4udRXgCNDH8+XXYmbTKw== X-Received: by 2002:a17:906:174f:b0:6d0:5629:e4be with SMTP id d15-20020a170906174f00b006d05629e4bemr139081eje.525.1645051555926; Wed, 16 Feb 2022 14:45:55 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-075-152.78.54.pool.telefonica.de. [78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:45:55 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 2/7] malta: Move PCI interrupt handling from gt64xxx_pci to piix4 Date: Wed, 16 Feb 2022 23:45:14 +0100 Message-Id: <20220216224519.157233-3-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::62c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Handling PCI interrupts in piix4 increases cohesion and reduces differences between piix4 and piix3. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 55 ++++++++++++++++++++++++++++++++++++++ hw/mips/gt64xxx_pci.c | 60 ++++-------------------------------------- hw/mips/malta.c | 6 +---- include/hw/mips/mips.h | 2 +- 4 files changed, 62 insertions(+), 61 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 0fe7b69bc4..196b56e69c 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -45,6 +45,7 @@ struct PIIX4State { PCIDevice dev; qemu_irq cpu_intr; qemu_irq *isa; + qemu_irq i8259[ISA_NUM_IRQS]; RTCState rtc; /* Reset Control Register */ @@ -54,6 +55,27 @@ struct PIIX4State { OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) +static void piix4_set_irq(void *opaque, int irq_num, int level) +{ + int i, pic_irq, pic_level; + qemu_irq *pic = opaque; + PCIBus *bus = pci_get_bus(piix4_dev); + + /* now we change the pic irq level according to the piix irq mappings */ + /* XXX: optimize */ + pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; + if (pic_irq < 16) { + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ + pic_level = 0; + for (i = 0; i < 4; i++) { + if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { + pic_level |= pci_bus_get_irq_level(bus, i); + } + } + qemu_set_irq(pic[pic_irq], pic_level); + } +} + static void piix4_isa_reset(DeviceState *dev) { PIIX4State *d = PIIX4_PCI_DEVICE(dev); @@ -248,8 +270,34 @@ static void piix4_register_types(void) type_init(piix4_register_types) +static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) +{ + int slot; + + slot = PCI_SLOT(pci_dev->devfn); + + switch (slot) { + /* PIIX4 USB */ + case 10: + return 3; + /* AMD 79C973 Ethernet */ + case 11: + return 1; + /* Crystal 4281 Sound */ + case 12: + return 2; + /* PCI slot 1 to 4 */ + case 18 ... 21: + return ((slot - 18) + irq_num) & 0x03; + /* Unknown device, don't do any translation */ + default: + return irq_num; + } +} + DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) { + PIIX4State *s; PCIDevice *pci; DeviceState *dev; int devfn = PCI_DEVFN(10, 0); @@ -257,6 +305,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci = pci_create_simple_multifunction(pci_bus, devfn, true, TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(pci); + s = PIIX4_PCI_DEVICE(pci); if (isa_bus) { *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); } @@ -271,5 +320,11 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->i8259, 4); + + for (int i = 0; i < ISA_NUM_IRQS; i++) { + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); + } + return dev; } diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 4cbd0911f5..eb205d6d70 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -29,7 +29,6 @@ #include "hw/mips/mips.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" -#include "hw/southbridge/piix.h" #include "migration/vmstate.h" #include "hw/intc/i8259.h" #include "hw/irq.h" @@ -981,53 +980,6 @@ static const MemoryRegionOps isd_mem_ops = { }, }; -static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) -{ - int slot; - - slot = PCI_SLOT(pci_dev->devfn); - - switch (slot) { - /* PIIX4 USB */ - case 10: - return 3; - /* AMD 79C973 Ethernet */ - case 11: - return 1; - /* Crystal 4281 Sound */ - case 12: - return 2; - /* PCI slot 1 to 4 */ - case 18 ... 21: - return ((slot - 18) + irq_num) & 0x03; - /* Unknown device, don't do any translation */ - default: - return irq_num; - } -} - -static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - qemu_irq *pic = opaque; - PCIBus *bus = pci_get_bus(piix4_dev); - - /* now we change the pic irq level according to the piix irq mappings */ - /* XXX: optimize */ - pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; - if (pic_irq < 16) { - /* The pic level is the logical OR of all the PCI irqs mapped to it. */ - pic_level = 0; - for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { - pic_level |= pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(pic[pic_irq], pic_level); - } -} - - static void gt64120_reset(DeviceState *dev) { GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); @@ -1204,7 +1156,7 @@ static void gt64120_realize(DeviceState *dev, Error **errp) "gt64120-isd", 0x1000); } -PCIBus *gt64120_register(qemu_irq *pic) +PCIBus *gt64120_register(void) { GT64120State *d; PCIHostState *phb; @@ -1215,12 +1167,10 @@ PCIBus *gt64120_register(qemu_irq *pic) phb = PCI_HOST_BRIDGE(dev); memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); - phb->bus = pci_register_root_bus(dev, "pci", - gt64120_pci_set_irq, gt64120_pci_map_irq, - pic, - &d->pci0_mem, - get_system_io(), - PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS); + phb->bus = pci_root_bus_new(dev, "pci", + &d->pci0_mem, + get_system_io(), + PCI_DEVFN(18, 0), TYPE_PCI_BUS); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index b770b8d367..13254dbc89 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -97,7 +97,6 @@ struct MaltaState { Clock *cpuclk; MIPSCPSState cps; - qemu_irq i8259[ISA_NUM_IRQS]; }; static struct _loaderparams { @@ -1391,7 +1390,7 @@ void mips_malta_init(MachineState *machine) stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); /* Northbridge */ - pci_bus = gt64120_register(s->i8259); + pci_bus = gt64120_register(); /* * The whole address space decoded by the GT-64120A doesn't generate * exception when accessing invalid memory. Create an empty slot to @@ -1404,9 +1403,6 @@ void mips_malta_init(MachineState *machine) /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); - for (int i = 0; i < ISA_NUM_IRQS; i++) { - s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); - } /* generate SPD EEPROM data */ generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size); diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index 6c9c8805f3..ff88942e63 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -10,7 +10,7 @@ #include "exec/memory.h" /* gt64xxx.c */ -PCIBus *gt64120_register(qemu_irq *pic); +PCIBus *gt64120_register(void); /* bonito.c */ PCIBus *bonito_init(qemu_irq *pic); From patchwork Wed Feb 16 22:45:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1593953 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=mpUn2rl3; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JzY8J50k7z9sFN for ; Thu, 17 Feb 2022 09:50:40 +1100 (AEDT) Received: from localhost ([::1]:37830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKT89-0004qh-Bj for incoming@patchwork.ozlabs.org; Wed, 16 Feb 2022 17:50:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39408) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKT3g-0007aJ-V3 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:46:01 -0500 Received: from [2a00:1450:4864:20::52a] (port=36451 helo=mail-ed1-x52a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nKT3f-0003Rr-0Q for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:46:00 -0500 Received: by mail-ed1-x52a.google.com with SMTP id t21so6441491edd.3 for ; Wed, 16 Feb 2022 14:45:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y629EjZYx2MpzBQL6ITTZb0sditZh+KDcoZphc9Zzko=; b=mpUn2rl3hJHZ4nq+KhJFN1j8qyXq0/HQ8EfpikcPzvJULZnCYfimR1W8Ur5vbiBomg RulyWQEW7ZexpsBHnxEr/ROrpuBgzRBE9kffABzln+AdHv81wai93s0dW/xYS69vTTdV 0LijC3cTcCH6s29q0aZFdpkSwX82XZXlIrh0s3iNCJOEApZEFkI43ys9k6u8XHhkyPmc d5KtczTAlXpSGWXVW0lO4cwEnyAQ+wKYiYZ3k2w+LKAfaxGHqQTdjYaJCdi/QYQDbC+w tnd+ikH89KaqnWvMSBZkqm+fzDSB51IHaRW7e581mtriFWKQAJcGt5Q41TtehA89gbAe tHug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y629EjZYx2MpzBQL6ITTZb0sditZh+KDcoZphc9Zzko=; b=AaJ/pKJUTczDpt4H6O2SrP9YihTAvKkRpaygfJWCr1ZdPNTvBnoZf3lRUNYQwilDar u3muj7OUpyqTaceofQvrTNpxdIC3p6OCnEG+IXmlca+aDr5QV3o9mkXDydIqxIsfqpQI hFyJ+IztXtv4u/3C2W3p1c7ywE+eGGTeflZ/bkd6MtuNRRMleXXYlfrgXgMvtlf060nw aXeIIKucMkWTx/q4YkEZh+b02BmBXgJtCpuwSuzLDz+3S3wcvtYitiIVeTaz32fXt2Zh KiVwcs2VXcfwI6XoIfEs4RbDqBWCKjEc0uIp0tQ+pUE8zSHpEJ857B+09aEbxZM8MfBE 4PbQ== X-Gm-Message-State: AOAM531HY8bHNlj3/lA7qtb6pDK38poEezuZc7P34MJC7wadd29dcuxS SNjQWBh2HcdXhu6rC9uiZXVdocpc55I= X-Google-Smtp-Source: ABdhPJy22eMugA9eedH0jCmkFXLA1Ub5G2zfigWZkLseYnXCVzj0IC+eg+F0NaFTlAHuYTw5q0/qOA== X-Received: by 2002:a50:da47:0:b0:410:a39a:c43b with SMTP id a7-20020a50da47000000b00410a39ac43bmr5495283edk.33.1645051557677; Wed, 16 Feb 2022 14:45:57 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-075-152.78.54.pool.telefonica.de. [78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:45:57 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute Date: Wed, 16 Feb 2022 23:45:15 +0100 Message-Id: <20220216224519.157233-4-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to PIIX4State to make the code movement more obvious. However, i8259[] seems redundant to *isa, so remove it. Signed-off-by: Bernhard Beschow Acked-by: Michael S. Tsirkin --- hw/isa/piix4.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 196b56e69c..179968b18e 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -45,7 +45,6 @@ struct PIIX4State { PCIDevice dev; qemu_irq cpu_intr; qemu_irq *isa; - qemu_irq i8259[ISA_NUM_IRQS]; RTCState rtc; /* Reset Control Register */ @@ -320,11 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->i8259, 4); - - for (int i = 0; i < ISA_NUM_IRQS; i++) { - s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); - } + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->isa, 4); return dev; } From patchwork Wed Feb 16 22:45:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1593948 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=IYVMHdrP; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JzY4t2PYKz9sFn for ; Thu, 17 Feb 2022 09:47:42 +1100 (AEDT) Received: from localhost ([::1]:57736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKT5H-0007fF-QX for incoming@patchwork.ozlabs.org; Wed, 16 Feb 2022 17:47:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKT3i-0007bI-3f for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:46:03 -0500 Received: from [2a00:1450:4864:20::62e] (port=41774 helo=mail-ej1-x62e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nKT3g-0003S3-Mg for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:46:01 -0500 Received: by mail-ej1-x62e.google.com with SMTP id a8so2559275ejc.8 for ; Wed, 16 Feb 2022 14:46:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rsH7psBDlNZ46FWkWuLCo+KqCVzav8ctlundqbcFfp8=; b=IYVMHdrPIxxGmVvTginocTtQV952330510rl0cFmuUhvfdJDwC728kGimyPG7Bhi6T WWvUzalH4i5Ii2Grb5ZRyWAABnCfShJXIOo3nUd7NwQiwlQGUOT+DhrzAckwegML9gtv VMw00g9uixkIy1kWipbU3UP8vvrb/Ha7hBnmi2T44DJMQtg9SEDcAldCgwqW13ktvNSP DPTcSuoQy7ZHI+xXaD+kKtGleq5Ls5fNyaHvlw75wAyGiV/EHOM7/c+gtsgeG3OnOnWI U2q2oerbNmw+rZcYm7FAILo0NPlvkumlyN/s4OkryADnFkRam2U60sY9opVlFjB3E1Mr LMCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rsH7psBDlNZ46FWkWuLCo+KqCVzav8ctlundqbcFfp8=; b=fkYFskDQT3vgLQPCPyaEFLQnE3sSU6zyy0uP7MBIwZB9d8PuYS5O8caQdiTjGcfbAW u1o4FV7DMdEzFfiwabXy6oIbrCM6mGgd1/9PTBps0Dut8oJB+Hxlt6LlRvoR1OH/4ftz uZVj1dcEU7ort9TPYLGuVs4Qm6kM5fLRW6Dhj0wYUmT1y5bKpPT20/GiOSuUHr2z3h6g 2BDVoeL0lxWtASVKx7uoOiTEDBuHSv/tx3CivZyDo5agS9wlDoUpT3jqeuzqMb3qxcdI /5WFcHlmqHUBwYwELqJPS2chhZgWVAUrOgSfhv/qTB1wNFLNQYyl3bow/04TleQzKg2s bi7A== X-Gm-Message-State: AOAM530UltNCEXWWcl0E+K4ZxzVTxXtW+P+LDVgSLY3pMiN5g+U98qGZ 8tETEZFDAYICqczt34PHkTsZeNFcqHI= X-Google-Smtp-Source: ABdhPJxKkalKww9hIXgmHJqB6KRzvSaRyU+TxVarNQQhbdq8BQAfTu3QBHRAW9BD6CLbiTDZJiJ9xw== X-Received: by 2002:a17:906:3905:b0:6cf:7ef5:fee0 with SMTP id f5-20020a170906390500b006cf7ef5fee0mr148614eje.307.1645051559377; Wed, 16 Feb 2022 14:45:59 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-075-152.78.54.pool.telefonica.de. [78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:45:59 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 4/7] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() Date: Wed, 16 Feb 2022 23:45:16 +0100 Message-Id: <20220216224519.157233-5-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::62e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Passing PIIX4State rather than just the qemu_irq allows for resolving the global piix4_dev variable. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin --- hw/isa/piix4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 179968b18e..caa2002e2c 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -57,7 +57,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - qemu_irq *pic = opaque; + PIIX4State *s = opaque; PCIBus *bus = pci_get_bus(piix4_dev); /* now we change the pic irq level according to the piix irq mappings */ @@ -71,7 +71,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) pic_level |= pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(pic[pic_irq], pic_level); + qemu_set_irq(s->isa[pic_irq], pic_level); } } @@ -319,7 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->isa, 4); + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4); return dev; } From patchwork Wed Feb 16 22:45:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1593956 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=TEL3bGyA; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JzYFq6xYwz9sFN for ; Thu, 17 Feb 2022 09:55:27 +1100 (AEDT) Received: from localhost ([::1]:48186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKTCn-0003d5-Qs for incoming@patchwork.ozlabs.org; Wed, 16 Feb 2022 17:55:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKT9m-0000xV-RE for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:52:18 -0500 Received: from [2a00:1450:4864:20::136] (port=42967 helo=mail-lf1-x136.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nKT9l-0004Qp-6x for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:52:18 -0500 Received: by mail-lf1-x136.google.com with SMTP id e5so6587056lfr.9 for ; Wed, 16 Feb 2022 14:52:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fR+hSpTVUnCA2HhlgC/TOPy1wuGqJeKHWsmQuOseKtM=; b=TEL3bGyAmQEcpGKCvJ4iKJbwFfdPAg1vduy/Sv8uyqt6H2S2lnIJFx+hqevUL3yN+t 4JdhR0sSc0d/eQn9LU9mSbo03EkOgaJJKRGjXRK3LjuKlL2zG4Yxo442AY1rmX8dG7/F VJtWBerk9rWMg+4jSVkpvO4pgYddOox0MqcmRW6TUhvfBANiF4JYh10rcQKzs1PLSO0k PcDMPco+hY+Y4IPyHAekkexm1WwmbXPh51sIZW7YW0WgKhdl+VL0JN14loCYkzj4kqYJ VLE7nDoXR6btjpMhS80bXS8Uf7srfGjNkG4J7oZZ+Y8Cw9LphmwcjB41UqNHknGnfzIT P5Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fR+hSpTVUnCA2HhlgC/TOPy1wuGqJeKHWsmQuOseKtM=; b=mezV1HkwDlbLoxoC5cMxLWTzUOyvZKTmdQJy0WE5oEnuBOMWApmp2unQ9CYscqUjIN MHLdsNSmg//wJV1uu8dPtZDQpUSd49yZjAzg0cN4Pf6qutdLdYn3vT/UuIgBXDoJ42o2 bPjiZViWAq8B3ijGQH/bR/l8R2BZo41b4WxbaqpJWR/iCoyuWX43qYQbjaIvlX4gzCLF rWZDl7dAOLd+KoVe4IHOaUo09hxPu/1YdcClPJvxsrBos6mjchFNkN9l16IhhpKQvC1X 6NdrVPbjaKZrQk/dGov+b7uf7J/zI6Mpehlrftk8yy3um1Lmjys8XRKbQCUyqmEla41o KpZQ== X-Gm-Message-State: AOAM5309KplEn3He6LpPruT1BOW6ZtCSPkWp3YOEf4VaGu5fPI7qpXy9 nn8kjl/RHwW345sovvhJDh6hiqgOuZU= X-Google-Smtp-Source: ABdhPJzyp6gztMFMkJUkB2mVbFp29gZVAVw00whdurJJ3SEepsUmBJH7FAFId5r/InUq4xfG+7Eevw== X-Received: by 2002:a17:907:c92:b0:6b5:c8ae:7918 with SMTP id gi18-20020a1709070c9200b006b5c8ae7918mr136550ejc.531.1645051560991; Wed, 16 Feb 2022 14:46:00 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-075-152.78.54.pool.telefonica.de. [78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:46:00 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 5/7] hw/isa/piix4: Resolve global instance variable Date: Wed, 16 Feb 2022 23:45:17 +0100 Message-Id: <20220216224519.157233-6-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::136 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=shentey@gmail.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , =?utf-8?q?Herv=C3=A9_Poussineau?= , Bernhard Beschow , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that piix4_set_irq's opaque parameter references own PIIX4State, piix4_dev becomes redundant. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin --- hw/isa/piix4.c | 10 +++------- include/hw/southbridge/piix.h | 2 -- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index caa2002e2c..2e9b5ccada 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -39,8 +39,6 @@ #include "sysemu/runstate.h" #include "qom/object.h" -PCIDevice *piix4_dev; - struct PIIX4State { PCIDevice dev; qemu_irq cpu_intr; @@ -58,16 +56,16 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; PIIX4State *s = opaque; - PCIBus *bus = pci_get_bus(piix4_dev); + PCIBus *bus = pci_get_bus(&s->dev); /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { pic_level |= pci_bus_get_irq_level(bus, i); } } @@ -219,8 +217,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); - - piix4_dev = dev; } static void piix4_init(Object *obj) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 6387f2b612..f63f83e5c6 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -70,8 +70,6 @@ typedef struct PIIXState PIIX3State; DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) -extern PCIDevice *piix4_dev; - PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus); From patchwork Wed Feb 16 22:45:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1593954 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; 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[78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:46:02 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants Date: Wed, 16 Feb 2022 23:45:18 +0100 Message-Id: <20220216224519.157233-7-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::62c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably didn't want to use piix4-specific constants. Now that the interrupt handing resides in piix4, its constants can be used. Signed-off-by: Bernhard Beschow Acked-by: Michael S. Tsirkin --- hw/isa/piix4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 2e9b5ccada..f876c71750 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -61,10 +61,10 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < 16) { + if (pic_irq < ISA_NUM_IRQS) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; - for (i = 0; i < 4; i++) { + for (i = 0; i < PIIX_NUM_PIRQS; i++) { if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { pic_level |= pci_bus_get_irq_level(bus, i); } @@ -315,7 +315,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4); + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); return dev; } From patchwork Wed Feb 16 22:45:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 1593955 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20210112 header.b=HwjKQVhQ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4JzYBy3bWwz9sFN for ; Thu, 17 Feb 2022 09:52:57 +1100 (AEDT) Received: from localhost ([::1]:44516 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nKTAM-00014N-24 for incoming@patchwork.ozlabs.org; Wed, 16 Feb 2022 17:52:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nKT3n-0007ms-Ie for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:46:07 -0500 Received: from [2a00:1450:4864:20::52d] (port=43647 helo=mail-ed1-x52d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nKT3l-0003SW-Q3 for qemu-devel@nongnu.org; Wed, 16 Feb 2022 17:46:07 -0500 Received: by mail-ed1-x52d.google.com with SMTP id m3so461565eda.10 for ; Wed, 16 Feb 2022 14:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WbIstrcYIVfKLpqcOPyh6SwNWQ33Mhi39mdw+dA+Tjs=; b=HwjKQVhQNcJY1eMOFVITUVcjcA0qMO+JE3PFPzzbSJ5YreeAoO1Fzo81dwuoO0Rb4E PlDN/Zj9tTOAJuqYamOECWeP8RjdYkBfwdPTSHZyARbPIObHOZNHQzv4Y8zZDyS7GI50 MJbeYxy6/07GLah8E1kX8MGpF3bmSX+kfsuggYCeKjZ4Boxsj6fjfLXR+2wAX8NT0Nlf ttsMRGfua2pBjTeQSZhX8BoRqJ0Rn9DzuiIVgghCe747cX3BcZAOkIccBFKGa5Pu4ins TV7B7kL/U/yzaA2brwKtwXMYVUPkFDdOZAcKSuoe4m+34VCfMfrNr2Rl4vnxDSoXllK9 bZ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WbIstrcYIVfKLpqcOPyh6SwNWQ33Mhi39mdw+dA+Tjs=; b=0oNVY4kpDuDWw9pw18caDAm7LOoOu4jR6hjkrQPJGGmA3CGXTsZEW7b9pbacG30S3p pbfhx+lFPG5mJF5uiABsJXEe8XwCARYp/OxOapYquXgH8IZ/dgulrRFB/txcjHYeRWD0 sIG18oQPhtKmXRviwrx3L4medXskKfvcVkTEnkt4Ra7OmgHSM+JXyISmqqbWLe+rnbbr fYA6TPJ22fjAXAN8iNAxGCh0Fo6qTXSnbYAuJrCjEahFbFK91Hin5LYZpNUSffirZi+s bdgEJrbO7bw3ptHHwQGhk7LjM2Y/NTbCEJ9HR81Eh4wOw7vW8g9KEfFj8I9p6OcIExCl jrkQ== X-Gm-Message-State: AOAM533Pu2/UJm0Tl2GwDskvmwu2A2HKl2AnvAIFJu5WtEepSC/biWrW uW9jMtCGqRz299ggFUULly4gyvEFv9Q= X-Google-Smtp-Source: ABdhPJwlq2KDi2XP0XHAeSWqrhPl0BnRz7slaoH5jWYbixBhclj1qj2qujShZLOQYG2QXefuyY0KZA== X-Received: by 2002:a05:6402:198:b0:410:83e3:21d7 with SMTP id r24-20020a056402019800b0041083e321d7mr5413988edv.159.1645051564464; Wed, 16 Feb 2022 14:46:04 -0800 (PST) Received: from Provence.localdomain (dynamic-078-054-075-152.78.54.pool.telefonica.de. [78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.46.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:46:04 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 7/7] hw/mips/gt64xxx_pci: Resolve gt64120_register() Date: Wed, 16 Feb 2022 23:45:19 +0100 Message-Id: <20220216224519.157233-8-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that gt64120_register() lost its pic parameter, there is an opportunity to remove it. gt64120_register() is old style by wrapping qdev API, and the new style is to use qdev directly. So take the opportunity and modernize the code. Suggested-by: BALATON Zoltan Signed-off-by: Bernhard Beschow --- hw/mips/gt64xxx_pci.c | 21 ++++----------------- hw/mips/malta.c | 13 ++++++++----- include/hw/mips/mips.h | 3 --- 3 files changed, 12 insertions(+), 25 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index eb205d6d70..e0ff1b5566 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -26,7 +26,6 @@ #include "qapi/error.h" #include "qemu/units.h" #include "qemu/log.h" -#include "hw/mips/mips.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "migration/vmstate.h" @@ -1151,30 +1150,18 @@ static void gt64120_reset(DeviceState *dev) static void gt64120_realize(DeviceState *dev, Error **errp) { GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); + PCIHostState *phb = PCI_HOST_BRIDGE(dev); memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s, "gt64120-isd", 0x1000); -} - -PCIBus *gt64120_register(void) -{ - GT64120State *d; - PCIHostState *phb; - DeviceState *dev; - - dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE); - d = GT64120_PCI_HOST_BRIDGE(dev); - phb = PCI_HOST_BRIDGE(dev); - memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); - address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem"); + memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB); + address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem"); phb->bus = pci_root_bus_new(dev, "pci", - &d->pci0_mem, + &s->pci0_mem, get_system_io(), PCI_DEVFN(18, 0), TYPE_PCI_BUS); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); - return phb->bus; } static void gt64120_pci_realize(PCIDevice *d, Error **errp) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 13254dbc89..16fdaed3db 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -38,6 +38,7 @@ #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_host.h" #include "qemu/log.h" #include "hw/mips/bios.h" #include "hw/ide.h" @@ -1230,7 +1231,7 @@ void mips_malta_init(MachineState *machine) const size_t smbus_eeprom_size = 8 * 256; uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); uint64_t kernel_entry, bootloader_run_addr; - PCIBus *pci_bus; + PCIHostState *phb; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; I2CBus *smbus; @@ -1390,7 +1391,9 @@ void mips_malta_init(MachineState *machine) stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); /* Northbridge */ - pci_bus = gt64120_register(); + dev = qdev_new("gt64120"); + phb = PCI_HOST_BRIDGE(dev); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* * The whole address space decoded by the GT-64120A doesn't generate * exception when accessing invalid memory. Create an empty slot to @@ -1399,7 +1402,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - dev = piix4_create(pci_bus, &isa_bus, &smbus); + dev = piix4_create(phb->bus, &isa_bus, &smbus); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); @@ -1414,10 +1417,10 @@ void mips_malta_init(MachineState *machine) isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO); /* Network card */ - network_init(pci_bus); + network_init(phb->bus); /* Optional PCI video card */ - pci_vga_init(pci_bus); + pci_vga_init(phb->bus); } static void mips_malta_instance_init(Object *obj) diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index ff88942e63..101799f7d3 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -9,9 +9,6 @@ #include "exec/memory.h" -/* gt64xxx.c */ -PCIBus *gt64120_register(void); - /* bonito.c */ PCIBus *bonito_init(qemu_irq *pic);