From patchwork Wed Oct 13 01:01:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1540076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Xa1tUKKw; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HTZ6w5qryz9t0T for ; Wed, 13 Oct 2021 12:04:08 +1100 (AEDT) Received: from localhost ([::1]:45520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maSgg-0003dM-Kf for incoming@patchwork.ozlabs.org; Tue, 12 Oct 2021 21:04:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maSeD-0007sl-Dg for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:33 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]:34714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maSeB-00055X-TU for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:33 -0400 Received: by mail-oi1-x231.google.com with SMTP id z11so1650319oih.1 for ; Tue, 12 Oct 2021 18:01:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u3mRe1SjnbN4eZ/xlikZ4lGZRr0bx5CMAJvP9b2L1LM=; b=Xa1tUKKw4kXBLRfsgySYj7ucRFjQ1LAN/1V6is6lTn+geg0H8d412sPcO+EaEc2h0R BkdOsrie9CBg3tzJWPwJXJU40RBUEXJnkCiAnM45Mq8Bg975/0fJNttAAIJxbxsUvHLm Tfg6hvYSaD15lvvx39/b9d19hViJuGLbu3ZPo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u3mRe1SjnbN4eZ/xlikZ4lGZRr0bx5CMAJvP9b2L1LM=; b=DumqOza18ttYY2cgt13nDdBiWPQM4mfYwHWmcdUlXjNbYlk8sEVkgglKG2bilXyOIV 6vgFG2qwX3toXw63jATrg5Shzi4wEqGXqZ80v6CHYw5Hdj3gmNWTFii+N0HJlkvnF3dB jjOd2EZWlyOAc2uTOiq0YrUgWMCU0xPCxdo6Bu1iXiDR0JUGOGK7hJOZlVEjg3Y30Ade TRoq5B770ltZQgOd5Y7v3FosjHpbxGSSlgI/dOVfa1xxhiDLqF/wb8s+YCLn0sDqkYi4 JKQEqcJSl/PRe8yW3wWX0zM49aoNW1MLymuMCH75RH/AEPZ007ezaIjb4mwsNjb5/o1O xIgg== X-Gm-Message-State: AOAM5317BK/Tjn/XpNCwhmrf+P2MXyxzn3ixDOGNA58EB2VcC9WrwSvM NDR5+ZKyIC4ttXWLQZ+WPn1iXw== X-Google-Smtp-Source: ABdhPJwNJvQsq38wNKSMBixWGzaiGqTvMOJMBZw5K6AZXQR3QfWLJRlJeFezA8WWiUrvdRMyMYecRQ== X-Received: by 2002:aca:a80c:: with SMTP id r12mr5968445oie.58.1634086890015; Tue, 12 Oct 2021 18:01:30 -0700 (PDT) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id a10sm238107otb.7.2021.10.12.18.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 18:01:29 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 01/16] arm: qemu: Mention -nographic in the docs Date: Tue, 12 Oct 2021 19:01:05 -0600 Message-Id: <20211013010120.96851-2-sjg@chromium.org> X-Mailer: git-send-email 2.33.0.882.g93a45727a2-goog In-Reply-To: <20211013010120.96851-1-sjg@chromium.org> References: <20211013010120.96851-1-sjg@chromium.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=sjg@chromium.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tom Rini , Simon Glass , Ilias Apalodimas , qemu-devel@nongnu.org, Albert Aribaud Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Without this option QEMU appears to hang. Add it to avoid confusion. Signed-off-by: Simon Glass --- doc/board/emulation/qemu-arm.rst | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 8d7fda10f15..97b6ec64905 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -41,14 +41,15 @@ The minimal QEMU command line to get U-Boot up and running is: - For ARM:: - qemu-system-arm -machine virt -bios u-boot.bin + qemu-system-arm -machine virt -nographic -bios u-boot.bin - For AArch64:: - qemu-system-aarch64 -machine virt -cpu cortex-a57 -bios u-boot.bin + qemu-system-aarch64 -machine virt -nographic -cpu cortex-a57 -bios u-boot.bin Note that for some odd reason qemu-system-aarch64 needs to be explicitly -told to use a 64-bit CPU or it will boot in 32-bit mode. +told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument +ensures that output appears on the terminal. Use Ctrl-A X to quit. Additional persistent U-boot environment support can be added as follows: From patchwork Wed Oct 13 01:01:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1540086 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=IULdiWfy; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HTZG94t2Pz9t0T for ; Wed, 13 Oct 2021 12:10:25 +1100 (AEDT) Received: from localhost ([::1]:54148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maSmk-0001HI-IC for incoming@patchwork.ozlabs.org; Tue, 12 Oct 2021 21:10:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39384) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maSeL-00085U-Ru for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:41 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]:39742) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maSeI-0005Cn-Sf for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:41 -0400 Received: by mail-oi1-x22a.google.com with SMTP id m67so1623226oif.6 for ; Tue, 12 Oct 2021 18:01:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sonr4+QlvB0BD70L0wqOWK7lNp2oGE8bokzvEATHsxw=; b=IULdiWfylgMEqb7ZX7WxrlbC7ZWz/4stAzDL1QEClcHsFz+WdykP7QLgtXvI8HgOye SYu0BQg9TGXBj7wtbD3MoGJW3VwTfVbNRGOn7t3n1cWcSTLxnzXp0ZG4FRh+qdVAYMwh I8FgqsL2YGzVANtJRb6BDmbZy8k5BZizDHZvo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sonr4+QlvB0BD70L0wqOWK7lNp2oGE8bokzvEATHsxw=; b=jiB1YHd/kxqbZVIodB1II4oSJ1NTciyh93TEDsnz3zVTLpWP0MvbnR6DILXJln1GSs Bw+SoPHw3U/QLT7nTZveJgyj6qDEoWxb5VZEYWJJlLbasQ9ioWl+5KR5tWYZPAekm/dB f59S3ik+fzn/9CXoqQZDlfEvS083j+qsxBUGy4D5MvfkRaHabwUP4Sh+ZgCYyL2Yola5 Mn6uQLv+sSY7aFe699WfrGfM6UWAv1xt/ENgpfezDI2aTB8TI6wYSiReQDxVFNTZbLNk X6o0IHlOZujUa/tz1ZWY1rbADBD/oecRns461B0TdudNnhF2sPtzO704CiQ09z7EoQal p8vg== X-Gm-Message-State: AOAM530OM4BXH3M9RBklmjziHN30z1g4AL1vYoNHFtzM5bf/VruOrHkt rEgEhcm110PbjGnHRORw89R1mw== X-Google-Smtp-Source: ABdhPJyzRRGmUw1PYMsQ8E4RUbqs0C3BPnGoY5PGZNZApFMbc67lS6kXNSXS+KXIitcpd38sLWiBwg== X-Received: by 2002:aca:c046:: with SMTP id q67mr5996611oif.33.1634086891402; Tue, 12 Oct 2021 18:01:31 -0700 (PDT) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id a10sm238107otb.7.2021.10.12.18.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 18:01:30 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 02/16] arm: qemu: Explain how to extract the generate devicetree Date: Tue, 12 Oct 2021 19:01:06 -0600 Message-Id: <20211013010120.96851-3-sjg@chromium.org> X-Mailer: git-send-email 2.33.0.882.g93a45727a2-goog In-Reply-To: <20211013010120.96851-1-sjg@chromium.org> References: <20211013010120.96851-1-sjg@chromium.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=sjg@chromium.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tom Rini , Simon Glass , Ilias Apalodimas , qemu-devel@nongnu.org, Albert Aribaud Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" QEMU currently generates a devicetree for use with U-Boot. Explain how to obtain it. Signed-off-by: Simon Glass --- doc/board/emulation/qemu-arm.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 97b6ec64905..b458a398c69 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -91,3 +91,15 @@ The debug UART on the ARM virt board uses these settings:: CONFIG_DEBUG_UART_PL010=y CONFIG_DEBUG_UART_BASE=0x9000000 CONFIG_DEBUG_UART_CLOCK=0 + +Obtaining the QEMU devicetree +----------------------------- + +QEMU generates its own devicetree to pass to U-Boot and does this by default. +You can use `-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version. + +To obtain the devicetree that qemu generates, add `-machine dumpdtb=dtb.dtb`, +e.g.:: + + qemu-system-aarch64 -machine virt -nographic -cpu cortex-a57 \ + -bios u-boot.bin -machine dumpdtb=dtb.dtb From patchwork Wed Oct 13 01:01:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1540084 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=FhEa3Fvx; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HTZ9B1pprz9t0T for ; Wed, 13 Oct 2021 12:06:06 +1100 (AEDT) Received: from localhost ([::1]:48280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maSia-0005Wv-2y for incoming@patchwork.ozlabs.org; Tue, 12 Oct 2021 21:06:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maSeG-0007wO-7x for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:36 -0400 Received: from mail-ot1-x330.google.com ([2607:f8b0:4864:20::330]:45737) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maSeE-0005A4-Ow for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:35 -0400 Received: by mail-ot1-x330.google.com with SMTP id l16-20020a9d6a90000000b0054e7ab56f27so1494276otq.12 for ; Tue, 12 Oct 2021 18:01:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xj1e/TwUMhnPg0EzSwAwQl/XvDUpfzlFFnWUPRvfKb0=; b=FhEa3FvxmdLpOq45YAjfZ9GlHPDA57GYj9Fd0qpKPJCNrdQ7i0Stg+HcMM7oplDcka 0uJVf3avJ+nutoLa/tPXFD6OsCqoNVc6gZpvvNI8uOERWSsWpWfNWqNzNX4dAJ61f6BJ 4yVGrN6Fy3VaGlwExiKpnFWK6M+LV31Tqnytk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xj1e/TwUMhnPg0EzSwAwQl/XvDUpfzlFFnWUPRvfKb0=; b=XxgAiSoDU3h9hAhW5xTDPdTphzEfj6W6P7wkWYQ5iFN/Yf4uE6ZNESDzLjoC8ZvtXw +z6g/I0Gw+JqR6XGdsqifxedK/Ajqbwt/lbF66i5DSAwonvkbc3HDDIDiXcVSx9Nqm3P JB62eVahgycR+1pP4VK6nzJvuye/ehR+wMgnH6NN9aY97allQObKb1MGX16/E9VjexA9 lFkKNu9KZOemoc5ZEs3kg+Ou5wt4JNdmg52n1KlZmP4R5BQCTEGXTlOaHlRohL5qK2II UfAsepOcQk24fvt8BkuejiF4x5oa8oYYtWu8K98IB4mNjsHGDZp5k06xMab0vE6gH9ok lLeA== X-Gm-Message-State: AOAM530Eymrt4XgaQ5bBI82Hszdz7UHwRQx9dhlS/erSuoqIRDc02Dk0 KOCl4JTOkM0P2uAytAdAA4n1Ew== X-Google-Smtp-Source: ABdhPJy0TemTw6auYJIG00wP8FppUlfLn32uE9pt8D9NiZN/nbvLYvGg4mQ+pn0GLW6kJh8t2B+1Xg== X-Received: by 2002:a9d:69c9:: with SMTP id v9mr28161771oto.127.1634086893619; Tue, 12 Oct 2021 18:01:33 -0700 (PDT) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id a10sm238107otb.7.2021.10.12.18.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 18:01:33 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 03/16] riscv: qemu: Explain how to extract the generate devicetree Date: Tue, 12 Oct 2021 19:01:07 -0600 Message-Id: <20211013010120.96851-4-sjg@chromium.org> X-Mailer: git-send-email 2.33.0.882.g93a45727a2-goog In-Reply-To: <20211013010120.96851-1-sjg@chromium.org> References: <20211013010120.96851-1-sjg@chromium.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=sjg@chromium.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tom Rini , Ilias Apalodimas , Heinrich Schuchardt , Simon Glass , Bin Meng , Rick Chen , qemu-devel@nongnu.org, Atish Patra Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" QEMU currently generates a devicetree for use with U-Boot. Explain how to obtain it. Signed-off-by: Simon Glass --- doc/board/emulation/qemu-riscv.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index 4b8e104a215..b3cf7085847 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -113,3 +113,15 @@ An attached disk can be emulated by adding:: -device ide-hd,drive=mydisk,bus=ahci.0 You will have to run 'scsi scan' to use it. + +Obtaining the QEMU devicetree +----------------------------- + +QEMU generates its own devicetree to pass to U-Boot and does this by default. +You can use `-dtb u-boot.dtb` to force QEMU to use U-Boot's in-tree version. + +To obtain the devicetree that qemu generates, add `-machine dumpdtb=dtb.dtb`, +e.g.:: + + qemu-system-riscv64 -nographic -machine virt -bios u-boot \ + -machine dumpdtb=dtb.dtb From patchwork Wed Oct 13 01:01:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1540085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=Se80Er7K; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HTZCV5CmTz9t0T for ; Wed, 13 Oct 2021 12:08:05 +1100 (AEDT) Received: from localhost ([::1]:51320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maSkU-0007ko-0L for incoming@patchwork.ozlabs.org; Tue, 12 Oct 2021 21:08:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1maSeI-00080B-5A for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:38 -0400 Received: from mail-ot1-x330.google.com ([2607:f8b0:4864:20::330]:46701) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1maSeG-0005BH-0v for qemu-devel@nongnu.org; Tue, 12 Oct 2021 21:01:37 -0400 Received: by mail-ot1-x330.google.com with SMTP id 62-20020a9d0a44000000b00552a6f8b804so948490otg.13 for ; Tue, 12 Oct 2021 18:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qs6OtSk6zJ9FRk9lRiM3peYXousM3D2wLYGHTF6JOlU=; b=Se80Er7KIwSBltydWwJdve2RDntBATdX57RMzbcPVEbObHrTa00YnZuUzrjHLiTKzb 00rUpKHfRyeBB3/aEs2hZzYnLlejFZ9t2uBSqxyKeNbQh0FkNcwkQ7jd308WqowZIH14 c105ZqZjPqpQMn6i2d1w+vx1JUsefRm2j1r04= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qs6OtSk6zJ9FRk9lRiM3peYXousM3D2wLYGHTF6JOlU=; b=qGYytr7qbHj/Gb39Zf8v+ICmFA1LC3xLWo4qtDTeLYzk3JStXyQtMRDs5EPGT/oChz J/xyJhGS5XIuMdfXvzl5fhol+HHHEmijyxVsRz8cFtbKzi3t5XcPscOsBRs23pXhA8gs zp3/Q4BAuQyXSvzOnbruIPyzaAbvGPiTDIZIzqiDBzusymlbRsXwu7L/N82XDKsdT/sh EgRI0aUmgvzDlBtqdA2hjnsxxv57n3ps6IMvQ7o9DDa8V3LoDGT4A6eV0Pn69BUJ7Rf1 qNrcDGZGMaRLNaMvuH0LkMTZ1CuS+G/Qz7Wt4+jlj7YNHFGl+H/Fc0kCED8KaBepGM6I MkMQ== X-Gm-Message-State: AOAM5336UhHYUYq3gJw6Mf64aNj0fYvkS3RLhD9IcXHMSbbkhfQ/91ZG 26KJ5XAziR9elpJvVxnxBbShdw== X-Google-Smtp-Source: ABdhPJxNgsDGT1BgL5NIFHnLs5exfG7EEgQJdTk1IisgLbPyDkvEtsjOkZnQqBVCb+Dm6FtlAIfiFQ== X-Received: by 2002:a05:6830:2258:: with SMTP id t24mr1383106otd.211.1634086894962; Tue, 12 Oct 2021 18:01:34 -0700 (PDT) Received: from kiwi.bld.corp.google.com (c-67-190-101-114.hsd1.co.comcast.net. [67.190.101.114]) by smtp.gmail.com with ESMTPSA id a10sm238107otb.7.2021.10.12.18.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 18:01:34 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 04/16] arm: qemu: Add a devicetree file for qemu_arm Date: Tue, 12 Oct 2021 19:01:08 -0600 Message-Id: <20211013010120.96851-5-sjg@chromium.org> X-Mailer: git-send-email 2.33.0.882.g93a45727a2-goog In-Reply-To: <20211013010120.96851-1-sjg@chromium.org> References: <20211013010120.96851-1-sjg@chromium.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=sjg@chromium.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tom Rini , Albert Aribaud , qemu-devel@nongnu.org, Andre Przywara , Simon Glass , Ilias Apalodimas , Christian Hewitt , Kever Yang , Rick Chen , Neil Armstrong , Tuomas Tynkkynen , Jagan Teki , Sean Anderson , Heiko Schocher , Fabio Estevam , Tim Harvey , Peter Robinson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add this file, generated from qemu, so there is a reference devicetree in the U-Boot tree. Signed-off-by: Simon Glass --- arch/arm/dts/Makefile | 2 + arch/arm/dts/qemu-arm.dts | 402 +++++++++++++++++++++++++++++++++++++ configs/qemu_arm_defconfig | 1 + 3 files changed, 405 insertions(+) create mode 100644 arch/arm/dts/qemu-arm.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8a382d1539..e2fc0cb65fc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1145,6 +1145,8 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb +dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/qemu-arm.dts b/arch/arm/dts/qemu-arm.dts new file mode 100644 index 00000000000..790571a9d9e --- /dev/null +++ b/arch/arm/dts/qemu-arm.dts @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Sample device tree for qemu_arm + + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { + interrupt-parent = <0x8001>; + #size-cells = <0x02>; + #address-cells = <0x02>; + compatible = "linux,dummy-virt"; + + psci { + migrate = <0x84000005>; + cpu_on = <0x84000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0x84000001>; + method = "hvc"; + compatible = "arm,psci-0.2\0arm,psci"; + }; + + memory@40000000 { + reg = <0x00 0x40000000 0x00 0x8000000>; + device_type = "memory"; + }; + + platform@c000000 { + interrupt-parent = <0x8001>; + ranges = <0x00 0x00 0xc000000 0x2000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "qemu,platform\0simple-bus"; + }; + + fw-cfg@9020000 { + dma-coherent; + reg = <0x00 0x9020000 0x00 0x18>; + compatible = "qemu,fw-cfg-mmio"; + }; + + virtio_mmio@a000000 { + dma-coherent; + interrupts = <0x00 0x10 0x01>; + reg = <0x00 0xa000000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000200 { + dma-coherent; + interrupts = <0x00 0x11 0x01>; + reg = <0x00 0xa000200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000400 { + dma-coherent; + interrupts = <0x00 0x12 0x01>; + reg = <0x00 0xa000400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000600 { + dma-coherent; + interrupts = <0x00 0x13 0x01>; + reg = <0x00 0xa000600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000800 { + dma-coherent; + interrupts = <0x00 0x14 0x01>; + reg = <0x00 0xa000800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000a00 { + dma-coherent; + interrupts = <0x00 0x15 0x01>; + reg = <0x00 0xa000a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000c00 { + dma-coherent; + interrupts = <0x00 0x16 0x01>; + reg = <0x00 0xa000c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000e00 { + dma-coherent; + interrupts = <0x00 0x17 0x01>; + reg = <0x00 0xa000e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001000 { + dma-coherent; + interrupts = <0x00 0x18 0x01>; + reg = <0x00 0xa001000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001200 { + dma-coherent; + interrupts = <0x00 0x19 0x01>; + reg = <0x00 0xa001200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001400 { + dma-coherent; + interrupts = <0x00 0x1a 0x01>; + reg = <0x00 0xa001400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001600 { + dma-coherent; + interrupts = <0x00 0x1b 0x01>; + reg = <0x00 0xa001600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001800 { + dma-coherent; + interrupts = <0x00 0x1c 0x01>; + reg = <0x00 0xa001800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001a00 { + dma-coherent; + interrupts = <0x00 0x1d 0x01>; + reg = <0x00 0xa001a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001c00 { + dma-coherent; + interrupts = <0x00 0x1e 0x01>; + reg = <0x00 0xa001c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001e00 { + dma-coherent; + interrupts = <0x00 0x1f 0x01>; + reg = <0x00 0xa001e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002000 { + dma-coherent; + interrupts = <0x00 0x20 0x01>; + reg = <0x00 0xa002000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002200 { + dma-coherent; + interrupts = <0x00 0x21 0x01>; + reg = <0x00 0xa002200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002400 { + dma-coherent; + interrupts = <0x00 0x22 0x01>; + reg = <0x00 0xa002400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002600 { + dma-coherent; + interrupts = <0x00 0x23 0x01>; + reg = <0x00 0xa002600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002800 { + dma-coherent; + interrupts = <0x00 0x24 0x01>; + reg = <0x00 0xa002800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002a00 { + dma-coherent; + interrupts = <0x00 0x25 0x01>; + reg = <0x00 0xa002a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002c00 { + dma-coherent; + interrupts = <0x00 0x26 0x01>; + reg = <0x00 0xa002c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002e00 { + dma-coherent; + interrupts = <0x00 0x27 0x01>; + reg = <0x00 0xa002e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003000 { + dma-coherent; + interrupts = <0x00 0x28 0x01>; + reg = <0x00 0xa003000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003200 { + dma-coherent; + interrupts = <0x00 0x29 0x01>; + reg = <0x00 0xa003200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003400 { + dma-coherent; + interrupts = <0x00 0x2a 0x01>; + reg = <0x00 0xa003400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003600 { + dma-coherent; + interrupts = <0x00 0x2b 0x01>; + reg = <0x00 0xa003600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003800 { + dma-coherent; + interrupts = <0x00 0x2c 0x01>; + reg = <0x00 0xa003800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003a00 { + dma-coherent; + interrupts = <0x00 0x2d 0x01>; + reg = <0x00 0xa003a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003c00 { + dma-coherent; + interrupts = <0x00 0x2e 0x01>; + reg = <0x00 0xa003c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003e00 { + dma-coherent; + interrupts = <0x00 0x2f 0x01>; + reg = <0x00 0xa003e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + gpio-keys { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "gpio-keys"; + + poweroff { + gpios = <0x8003 0x03 0x00>; + linux,code = <0x74>; + label = "GPIO Key Poweroff"; + }; + }; + + pl061@9030000 { + phandle = <0x8003>; + clock-names = "apb_pclk"; + clocks = <0x8000>; + interrupts = <0x00 0x07 0x04>; + gpio-controller; + #gpio-cells = <0x02>; + compatible = "arm,pl061\0arm,primecell"; + reg = <0x00 0x9030000 0x00 0x1000>; + }; + + pcie@10000000 { + interrupt-map-mask = <0x1800 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x03 0x04 0x00 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x04 0x04 0x00 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x05 0x04 0x00 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x06 0x04 + 0x800 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x04 0x04 0x800 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x05 0x04 0x800 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x06 0x04 0x800 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x03 0x04 + 0x1000 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x05 0x04 0x1000 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x06 0x04 0x1000 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x03 0x04 0x1000 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x04 0x04 + 0x1800 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x06 0x04 0x1800 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x03 0x04 0x1800 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x04 0x04 0x1800 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x05 0x04>; + #interrupt-cells = <0x01>; + ranges = <0x1000000 0x00 0x00 0x00 + 0x3eff0000 0x00 0x10000 0x2000000 + 0x00 0x10000000 0x00 0x10000000 + 0x00 0x2eff0000 0x3000000 0x80 + 0x00 0x80 0x00 0x80 + 0x00>; + reg = <0x00 0x3f000000 0x00 0x1000000>; + msi-parent = <0x8002>; + dma-coherent; + bus-range = <0x00 0x0f>; + linux,pci-domain = <0x00>; + #size-cells = <0x02>; + #address-cells = <0x03>; + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + }; + + pl031@9010000 { + clock-names = "apb_pclk"; + clocks = <0x8000>; + interrupts = <0x00 0x02 0x04>; + reg = <0x00 0x9010000 0x00 0x1000>; + compatible = "arm,pl031\0arm,primecell"; + }; + + pl011@9000000 { + clock-names = "uartclk\0apb_pclk"; + clocks = <0x8000 0x8000>; + interrupts = <0x00 0x01 0x04>; + reg = <0x00 0x9000000 0x00 0x1000>; + compatible = "arm,pl011\0arm,primecell"; + }; + + pmu { + }; + + intc@8000000 { + phandle = <0x8001>; + reg = <0x00 0x8000000 0x00 0x10000 0x00 0x8010000 0x00 0x10000>; + compatible = "arm,cortex-a15-gic"; + ranges; + #size-cells = <0x02>; + #address-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x03>; + + v2m@8020000 { + phandle = <0x8002>; + reg = <0x00 0x8020000 0x00 0x1000>; + msi-controller; + compatible = "arm,gic-v2m-frame"; + }; + }; + + flash@0 { + bank-width = <0x04>; + reg = <0x00 0x00 0x00 0x4000000 0x00 0x4000000 0x00 0x4000000>; + compatible = "cfi-flash"; + }; + + cpus { + #size-cells = <0x00>; + #address-cells = <0x01>; + + cpu@0 { + reg = <0x00>; + compatible = "arm,cortex-a15"; + device_type = "cpu"; + }; + }; + + timer { + interrupts = <0x01 0x0d 0x104 0x01 0x0e 0x104 0x01 0x0b 0x104 0x01 0x0a 0x104>; + always-on; + compatible = "arm,armv7-timer"; + }; + + apb-pclk { + phandle = <0x8000>; + clock-output-names = "clk24mhz"; + clock-frequency = <0x16e3600>; + #clock-cells = <0x00>; + compatible = "fixed-clock"; + }; + + chosen { + stdout-path = "/pl011@9000000"; + }; +}; diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index ded58d387ad..81ca4ca9166 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -5,6 +5,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-arm" CONFIG_TARGET_QEMU_ARM_32BIT=y CONFIG_ARMV7_LPAE=y CONFIG_AHCI=y From patchwork Wed Oct 13 01:01:09 2021 Content-Type: text/plain; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id a10sm238107otb.7.2021.10.12.18.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 18:01:35 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 05/16] arm: qemu: Add a devicetree file for qemu_arm64 Date: Tue, 12 Oct 2021 19:01:09 -0600 Message-Id: <20211013010120.96851-6-sjg@chromium.org> X-Mailer: git-send-email 2.33.0.882.g93a45727a2-goog In-Reply-To: <20211013010120.96851-1-sjg@chromium.org> References: <20211013010120.96851-1-sjg@chromium.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=sjg@chromium.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tom Rini , Albert Aribaud , qemu-devel@nongnu.org, Andre Przywara , Simon Glass , Ilias Apalodimas , Christian Hewitt , Kever Yang , Rick Chen , Neil Armstrong , Tuomas Tynkkynen , Jagan Teki , Sean Anderson , Heiko Schocher , Fabio Estevam , Tim Harvey , Peter Robinson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add this file, generated from qemu, so there is a reference devicetree in the U-Boot tree. Signed-off-by: Simon Glass --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/qemu-arm64.dts | 381 +++++++++++++++++++++++++++++++++++ configs/qemu_arm64_defconfig | 1 + 3 files changed, 383 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/qemu-arm64.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e2fc0cb65fc..52c586f3974 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1145,7 +1145,7 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb -dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb +dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb targets += $(dtb-y) diff --git a/arch/arm/dts/qemu-arm64.dts b/arch/arm/dts/qemu-arm64.dts new file mode 100644 index 00000000000..7590e49cc84 --- /dev/null +++ b/arch/arm/dts/qemu-arm64.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Sample device tree for qemu_arm64 + + * Copyright 2021 Google LLC + */ + +/dts-v1/; + +/ { + interrupt-parent = <0x8001>; + #size-cells = <0x02>; + #address-cells = <0x02>; + compatible = "linux,dummy-virt"; + + psci { + migrate = <0xc4000005>; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + method = "hvc"; + compatible = "arm,psci-0.2\0arm,psci"; + }; + + memory@40000000 { + reg = <0x00 0x40000000 0x00 0x8000000>; + device_type = "memory"; + }; + + platform@c000000 { + interrupt-parent = <0x8001>; + ranges = <0x00 0x00 0xc000000 0x2000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "qemu,platform\0simple-bus"; + }; + + fw-cfg@9020000 { + dma-coherent; + reg = <0x00 0x9020000 0x00 0x18>; + compatible = "qemu,fw-cfg-mmio"; + }; + + virtio_mmio@a000000 { + dma-coherent; + interrupts = <0x00 0x10 0x01>; + reg = <0x00 0xa000000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000200 { + dma-coherent; + interrupts = <0x00 0x11 0x01>; + reg = <0x00 0xa000200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000400 { + dma-coherent; + interrupts = <0x00 0x12 0x01>; + reg = <0x00 0xa000400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000600 { + dma-coherent; + interrupts = <0x00 0x13 0x01>; + reg = <0x00 0xa000600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000800 { + dma-coherent; + interrupts = <0x00 0x14 0x01>; + reg = <0x00 0xa000800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000a00 { + dma-coherent; + interrupts = <0x00 0x15 0x01>; + reg = <0x00 0xa000a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000c00 { + dma-coherent; + interrupts = <0x00 0x16 0x01>; + reg = <0x00 0xa000c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a000e00 { + dma-coherent; + interrupts = <0x00 0x17 0x01>; + reg = <0x00 0xa000e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001000 { + dma-coherent; + interrupts = <0x00 0x18 0x01>; + reg = <0x00 0xa001000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001200 { + dma-coherent; + interrupts = <0x00 0x19 0x01>; + reg = <0x00 0xa001200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001400 { + dma-coherent; + interrupts = <0x00 0x1a 0x01>; + reg = <0x00 0xa001400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001600 { + dma-coherent; + interrupts = <0x00 0x1b 0x01>; + reg = <0x00 0xa001600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001800 { + dma-coherent; + interrupts = <0x00 0x1c 0x01>; + reg = <0x00 0xa001800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001a00 { + dma-coherent; + interrupts = <0x00 0x1d 0x01>; + reg = <0x00 0xa001a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001c00 { + dma-coherent; + interrupts = <0x00 0x1e 0x01>; + reg = <0x00 0xa001c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a001e00 { + dma-coherent; + interrupts = <0x00 0x1f 0x01>; + reg = <0x00 0xa001e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002000 { + dma-coherent; + interrupts = <0x00 0x20 0x01>; + reg = <0x00 0xa002000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002200 { + dma-coherent; + interrupts = <0x00 0x21 0x01>; + reg = <0x00 0xa002200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002400 { + dma-coherent; + interrupts = <0x00 0x22 0x01>; + reg = <0x00 0xa002400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002600 { + dma-coherent; + interrupts = <0x00 0x23 0x01>; + reg = <0x00 0xa002600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002800 { + dma-coherent; + interrupts = <0x00 0x24 0x01>; + reg = <0x00 0xa002800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002a00 { + dma-coherent; + interrupts = <0x00 0x25 0x01>; + reg = <0x00 0xa002a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002c00 { + dma-coherent; + interrupts = <0x00 0x26 0x01>; + reg = <0x00 0xa002c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a002e00 { + dma-coherent; + interrupts = <0x00 0x27 0x01>; + reg = <0x00 0xa002e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003000 { + dma-coherent; + interrupts = <0x00 0x28 0x01>; + reg = <0x00 0xa003000 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003200 { + dma-coherent; + interrupts = <0x00 0x29 0x01>; + reg = <0x00 0xa003200 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003400 { + dma-coherent; + interrupts = <0x00 0x2a 0x01>; + reg = <0x00 0xa003400 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003600 { + dma-coherent; + interrupts = <0x00 0x2b 0x01>; + reg = <0x00 0xa003600 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003800 { + dma-coherent; + interrupts = <0x00 0x2c 0x01>; + reg = <0x00 0xa003800 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003a00 { + dma-coherent; + interrupts = <0x00 0x2d 0x01>; + reg = <0x00 0xa003a00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003c00 { + dma-coherent; + interrupts = <0x00 0x2e 0x01>; + reg = <0x00 0xa003c00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@a003e00 { + dma-coherent; + interrupts = <0x00 0x2f 0x01>; + reg = <0x00 0xa003e00 0x00 0x200>; + compatible = "virtio,mmio"; + }; + + pcie@10000000 { + interrupt-map-mask = <0x1800 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x03 0x04 0x00 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x04 0x04 0x00 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x05 0x04 0x00 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x06 0x04 + 0x800 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x04 0x04 0x800 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x05 0x04 0x800 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x06 0x04 0x800 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x03 0x04 + 0x1000 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x05 0x04 0x1000 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x06 0x04 0x1000 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x03 0x04 0x1000 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x04 0x04 + 0x1800 0x00 0x00 0x01 0x8001 0x00 0x00 0x00 + 0x06 0x04 0x1800 0x00 0x00 0x02 0x8001 0x00 + 0x00 0x00 0x03 0x04 0x1800 0x00 0x00 0x03 + 0x8001 0x00 0x00 0x00 0x04 0x04 0x1800 0x00 + 0x00 0x04 0x8001 0x00 0x00 0x00 0x05 0x04>; + #interrupt-cells = <0x01>; + ranges = <0x1000000 0x00 0x00 0x00 + 0x3eff0000 0x00 0x10000 0x2000000 + 0x00 0x10000000 0x00 0x10000000 + 0x00 0x2eff0000 0x3000000 0x80 + 0x00 0x80 0x00 0x80 + 0x00>; + reg = <0x40 0x10000000 0x00 0x10000000>; + msi-parent = <0x8002>; + dma-coherent; + bus-range = <0x00 0xff>; + linux,pci-domain = <0x00>; + #size-cells = <0x02>; + #address-cells = <0x03>; + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + }; + + pl031@9010000 { + clock-names = "apb_pclk"; + clocks = <0x8000>; + interrupts = <0x00 0x02 0x04>; + reg = <0x00 0x9010000 0x00 0x1000>; + compatible = "arm,pl031\0arm,primecell"; + }; + + pl011@9000000 { + clock-names = "uartclk\0apb_pclk"; + clocks = <0x8000 0x8000>; + interrupts = <0x00 0x01 0x04>; + reg = <0x00 0x9000000 0x00 0x1000>; + compatible = "arm,pl011\0arm,primecell"; + }; + + pmu { + interrupts = <0x01 0x07 0x104>; + compatible = "arm,armv8-pmuv3"; + }; + + intc@8000000 { + phandle = <0x8001>; + reg = <0x00 0x8000000 0x00 0x10000 0x00 0x8010000 0x00 0x10000>; + compatible = "arm,cortex-a15-gic"; + ranges; + #size-cells = <0x02>; + #address-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x03>; + + v2m@8020000 { + phandle = <0x8002>; + reg = <0x00 0x8020000 0x00 0x1000>; + msi-controller; + compatible = "arm,gic-v2m-frame"; + }; + }; + + flash@0 { + bank-width = <0x04>; + reg = <0x00 0x00 0x00 0x4000000 0x00 0x4000000 0x00 0x4000000>; + compatible = "cfi-flash"; + }; + + cpus { + #size-cells = <0x00>; + #address-cells = <0x01>; + + cpu@0 { + reg = <0x00>; + compatible = "arm,cortex-a57"; + device_type = "cpu"; + }; + }; + + timer { + interrupts = <0x01 0x0d 0x104 0x01 0x0e 0x104 0x01 0x0b 0x104 0x01 0x0a 0x104>; + always-on; + compatible = "arm,armv8-timer\0arm,armv7-timer"; + }; + + apb-pclk { + phandle = <0x8000>; + clock-output-names = "clk24mhz"; + clock-frequency = <0x16e3600>; + #clock-cells = <0x00>; + compatible = "fixed-clock"; + }; + + chosen { + stdout-path = "/pl011@9000000"; + }; +}; diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index cf5a03e8a2f..e51ce5c799f 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -5,6 +5,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-arm64" CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x40200000 From patchwork Wed Oct 13 01:01:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1540068 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=BbE6++N4; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HTZ5912pgz9t0T for ; Wed, 13 Oct 2021 12:02:37 +1100 (AEDT) Received: from localhost ([::1]:39962 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1maSfC-00089C-Ry for incoming@patchwork.ozlabs.org; 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[67.190.101.114]) by smtp.gmail.com with ESMTPSA id a10sm238107otb.7.2021.10.12.18.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 18:01:37 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Subject: [PATCH 06/16] riscv: qemu: Add devicetree files for qemu_riscv32/64 Date: Tue, 12 Oct 2021 19:01:10 -0600 Message-Id: <20211013010120.96851-7-sjg@chromium.org> X-Mailer: git-send-email 2.33.0.882.g93a45727a2-goog In-Reply-To: <20211013010120.96851-1-sjg@chromium.org> References: <20211013010120.96851-1-sjg@chromium.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=sjg@chromium.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.049, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tom Rini , qemu-devel@nongnu.org, Leo , David Abdurachmanov , Simon Glass , Ilias Apalodimas , Rick Chen , Green Wan , Sean Anderson , Heinrich Schuchardt , Zong Li , Tianrui Wei , Bin Meng , Dimitri John Ledkov , Padmarao Begari Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add these files, generated from qemu, so there is a reference devicetree in the U-Boot tree. Split the existing qemu-virt into two, since we need a different devicetree for 32- and 64-bit machines. Signed-off-by: Simon Glass --- arch/riscv/dts/Makefile | 2 +- arch/riscv/dts/qemu-virt.dts | 8 - arch/riscv/dts/qemu-virt32.dts | 217 +++++++++++++++++++++++++++ arch/riscv/dts/qemu-virt64.dts | 217 +++++++++++++++++++++++++++ configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 2 +- configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 2 +- 10 files changed, 441 insertions(+), 11 deletions(-) delete mode 100644 arch/riscv/dts/qemu-virt.dts create mode 100644 arch/riscv/dts/qemu-virt32.dts create mode 100644 arch/riscv/dts/qemu-virt64.dts diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index b6e9166767b..90d3f35e6e3 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -2,7 +2,7 @@ dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb -dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb +dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt.dts deleted file mode 100644 index fecff542b91..00000000000 --- a/arch/riscv/dts/qemu-virt.dts +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2021, Bin Meng - */ - -/dts-v1/; - -#include "binman.dtsi" diff --git a/arch/riscv/dts/qemu-virt32.dts b/arch/riscv/dts/qemu-virt32.dts new file mode 100644 index 00000000000..3c449413523 --- /dev/null +++ b/arch/riscv/dts/qemu-virt32.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Bin Meng + */ + +/dts-v1/; + +#include "binman.dtsi" + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "riscv-virtio"; + model = "riscv-virtio,qemu"; + + fw-cfg@10100000 { + dma-coherent; + reg = <0x00 0x10100000 0x00 0x18>; + compatible = "qemu,fw-cfg-mmio"; + }; + + flash@20000000 { + bank-width = <0x04>; + reg = <0x00 0x20000000 0x00 0x2000000 + 0x00 0x22000000 0x00 0x2000000>; + compatible = "cfi-flash"; + }; + + chosen { + bootargs = [00]; + stdout-path = "/soc/uart@10000000"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0x989680>; + + cpu@0 { + phandle = <0x01>; + device_type = "cpu"; + reg = <0x00>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv32imafdcsu"; + mmu-type = "riscv,sv32"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x02>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x01>; + }; + }; + }; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; + + rtc@101000 { + interrupts = <0x0b>; + interrupt-parent = <0x03>; + reg = <0x00 0x101000 0x00 0x1000>; + compatible = "google,goldfish-rtc"; + }; + + uart@10000000 { + interrupts = <0x0a>; + interrupt-parent = <0x03>; + clock-frequency = <0x384000>; + reg = <0x00 0x10000000 0x00 0x100>; + compatible = "ns16550a"; + }; + + poweroff { + value = <0x5555>; + offset = <0x00>; + regmap = <0x04>; + compatible = "syscon-poweroff"; + }; + + reboot { + value = <0x7777>; + offset = <0x00>; + regmap = <0x04>; + compatible = "syscon-reboot"; + }; + + test@100000 { + phandle = <0x04>; + reg = <0x00 0x100000 0x00 0x1000>; + compatible = "sifive,test1\0sifive,test0\0syscon"; + }; + + pci@30000000 { + interrupt-map-mask = <0x1800 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00 + 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03 + 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23 + 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00 + 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03 + 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20 + 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00 + 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03 + 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21 + 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00 + 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03 + 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>; + ranges = <0x1000000 0x00 0x00 0x00 + 0x3000000 0x00 0x10000 0x2000000 + 0x00 0x40000000 0x00 0x40000000 + 0x00 0x40000000 0x3000000 0x03 + 0x00 0x03 0x00 0x01 + 0x00>; + reg = <0x00 0x30000000 0x00 0x10000000>; + dma-coherent; + bus-range = <0x00 0xff>; + linux,pci-domain = <0x00>; + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + #size-cells = <0x02>; + #interrupt-cells = <0x01>; + #address-cells = <0x03>; + }; + + virtio_mmio@10008000 { + interrupts = <0x08>; + interrupt-parent = <0x03>; + reg = <0x00 0x10008000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts = <0x07>; + interrupt-parent = <0x03>; + reg = <0x00 0x10007000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10006000 { + interrupts = <0x06>; + interrupt-parent = <0x03>; + reg = <0x00 0x10006000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10005000 { + interrupts = <0x05>; + interrupt-parent = <0x03>; + reg = <0x00 0x10005000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10004000 { + interrupts = <0x04>; + interrupt-parent = <0x03>; + reg = <0x00 0x10004000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10003000 { + interrupts = <0x03>; + interrupt-parent = <0x03>; + reg = <0x00 0x10003000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10002000 { + interrupts = <0x02>; + interrupt-parent = <0x03>; + reg = <0x00 0x10002000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10001000 { + interrupts = <0x01>; + interrupt-parent = <0x03>; + reg = <0x00 0x10001000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + plic@c000000 { + phandle = <0x03>; + riscv,ndev = <0x35>; + reg = <0x00 0xc000000 0x00 0x210000>; + interrupts-extended = <0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible = "sifive,plic-1.0.0\0riscv,plic0"; + #interrupt-cells = <0x01>; + #address-cells = <0x00>; + }; + + clint@2000000 { + interrupts-extended = <0x02 0x03 0x02 0x07>; + reg = <0x00 0x2000000 0x00 0x10000>; + compatible = "sifive,clint0\0riscv,clint0"; + }; + }; +}; diff --git a/arch/riscv/dts/qemu-virt64.dts b/arch/riscv/dts/qemu-virt64.dts new file mode 100644 index 00000000000..61bc084e280 --- /dev/null +++ b/arch/riscv/dts/qemu-virt64.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Bin Meng + */ + +/dts-v1/; + +#include "binman.dtsi" + +/ { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "riscv-virtio"; + model = "riscv-virtio,qemu"; + + fw-cfg@10100000 { + dma-coherent; + reg = <0x00 0x10100000 0x00 0x18>; + compatible = "qemu,fw-cfg-mmio"; + }; + + flash@20000000 { + bank-width = <0x04>; + reg = <0x00 0x20000000 0x00 0x2000000 + 0x00 0x22000000 0x00 0x2000000>; + compatible = "cfi-flash"; + }; + + chosen { + bootargs = [00]; + stdout-path = "/soc/uart@10000000"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x8000000>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + timebase-frequency = <0x989680>; + + cpu@0 { + phandle = <0x01>; + device_type = "cpu"; + reg = <0x00>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdcsu"; + mmu-type = "riscv,sv48"; + + interrupt-controller { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + phandle = <0x02>; + }; + }; + + cpu-map { + + cluster0 { + + core0 { + cpu = <0x01>; + }; + }; + }; + }; + + soc { + #address-cells = <0x02>; + #size-cells = <0x02>; + compatible = "simple-bus"; + ranges; + + rtc@101000 { + interrupts = <0x0b>; + interrupt-parent = <0x03>; + reg = <0x00 0x101000 0x00 0x1000>; + compatible = "google,goldfish-rtc"; + }; + + uart@10000000 { + interrupts = <0x0a>; + interrupt-parent = <0x03>; + clock-frequency = <0x384000>; + reg = <0x00 0x10000000 0x00 0x100>; + compatible = "ns16550a"; + }; + + poweroff { + value = <0x5555>; + offset = <0x00>; + regmap = <0x04>; + compatible = "syscon-poweroff"; + }; + + reboot { + value = <0x7777>; + offset = <0x00>; + regmap = <0x04>; + compatible = "syscon-reboot"; + }; + + test@100000 { + phandle = <0x04>; + reg = <0x00 0x100000 0x00 0x1000>; + compatible = "sifive,test1\0sifive,test0\0syscon"; + }; + + pci@30000000 { + interrupt-map-mask = <0x1800 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00 + 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03 + 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23 + 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00 + 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03 + 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20 + 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00 + 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03 + 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21 + 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00 + 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03 + 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>; + ranges = <0x1000000 0x00 0x00 0x00 + 0x3000000 0x00 0x10000 0x2000000 + 0x00 0x40000000 0x00 0x40000000 + 0x00 0x40000000 0x3000000 0x03 + 0x00 0x03 0x00 0x01 + 0x00>; + reg = <0x00 0x30000000 0x00 0x10000000>; + dma-coherent; + bus-range = <0x00 0xff>; + linux,pci-domain = <0x00>; + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + #size-cells = <0x02>; + #interrupt-cells = <0x01>; + #address-cells = <0x03>; + }; + + virtio_mmio@10008000 { + interrupts = <0x08>; + interrupt-parent = <0x03>; + reg = <0x00 0x10008000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10007000 { + interrupts = <0x07>; + interrupt-parent = <0x03>; + reg = <0x00 0x10007000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10006000 { + interrupts = <0x06>; + interrupt-parent = <0x03>; + reg = <0x00 0x10006000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10005000 { + interrupts = <0x05>; + interrupt-parent = <0x03>; + reg = <0x00 0x10005000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10004000 { + interrupts = <0x04>; + interrupt-parent = <0x03>; + reg = <0x00 0x10004000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10003000 { + interrupts = <0x03>; + interrupt-parent = <0x03>; + reg = <0x00 0x10003000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10002000 { + interrupts = <0x02>; + interrupt-parent = <0x03>; + reg = <0x00 0x10002000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + virtio_mmio@10001000 { + interrupts = <0x01>; + interrupt-parent = <0x03>; + reg = <0x00 0x10001000 0x00 0x1000>; + compatible = "virtio,mmio"; + }; + + plic@c000000 { + phandle = <0x03>; + riscv,ndev = <0x35>; + reg = <0x00 0xc000000 0x00 0x210000>; + interrupts-extended = <0x02 0x0b 0x02 0x09>; + interrupt-controller; + compatible = "sifive,plic-1.0.0\0riscv,plic0"; + #interrupt-cells = <0x01>; + #address-cells = <0x00>; + }; + + clint@2000000 { + interrupts-extended = <0x02 0x03 0x02 0x07>; + reg = <0x00 0x2000000 0x00 0x10000>; + compatible = "sifive,clint0\0riscv,clint0"; + }; + }; +}; diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index e77e3ed53a0..54953cd347b 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_TARGET_QEMU_VIRT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_LOAD_ADDR=0x80200000 diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 03787416f10..21ee08a643e 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index b0e655be416..3909c9a15ad 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -2,7 +2,7 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 1f8dc2d2053..303ad2d5f39 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index bdcec1fdaba..62cdf91699f 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -2,6 +2,7 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 9745c1a586a..34d88da41b0 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -2,7 +2,7 @@ CONFIG_RISCV=y CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_DEFAULT_DEVICE_TREE="qemu-virt" +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y