From patchwork Wed Oct 14 17:01:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 1382266 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=XpqNSJ9u; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CBJfp5Lxjz9sTK for ; Thu, 15 Oct 2020 04:04:18 +1100 (AEDT) Received: from localhost ([::1]:41006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kSkCG-0004KG-N9 for incoming@patchwork.ozlabs.org; Wed, 14 Oct 2020 13:04:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kSkAJ-0002kZ-GJ; Wed, 14 Oct 2020 13:02:15 -0400 Received: from mail-ed1-x542.google.com ([2a00:1450:4864:20::542]:37031) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kSkAH-0000nV-FA; Wed, 14 Oct 2020 13:02:15 -0400 Received: by mail-ed1-x542.google.com with SMTP id o18so210690edq.4; Wed, 14 Oct 2020 10:02:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aJ0KQb6Ozzm+TKAEStsx77t+LpGGqIZVP5UuxdMy3MY=; b=XpqNSJ9ujbXfuJhTtjLOFcHXa52vlNLLRyjRy2EvXJL+QNSwZONNGN3tdQfgKZDDZ/ 8ll0PCZksSOmgrK4pb5kXdncWID3UzRtmMRG+Uz1U8lZM69o1pdynWRixKNzLPuVe1pi 8EHh4hag+Xh27lXk6tXylovn2feSgr+iTOmfle50e1/OTUMpi4SVcIozorPhoNC2k5xX TOtN9WzwcozT2eoTMbeAhE/0dVNU/HPB0EizXoQF8g878BO22sGTF0l3HTR6qsbwy6B9 rcPnRXMZMM9m4H0Ok8lVxoRVVe48lWohRaTdtAmhVUOgRF3I3hA2ac3DY613x/Eu5EZO YXLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aJ0KQb6Ozzm+TKAEStsx77t+LpGGqIZVP5UuxdMy3MY=; b=cZUy5Hle4iNmIk81dnaVJ2u/Qt7e+P1sQ/wIA9vtxti3xLSLvC+H5m9eOKs+6o15jY fKt28OgWQSYJkJgH2/jLp2+9tV9R+kVYgjNlnFSM8aL3gLmYcAJucfv45BHUDl/rY8ob wOtJ4fRWuwAmDDs0c+da2VUgUcfHBwLXZcSCS+ZSL5v3IqKHTcurh7R/lBCLozREpjby d5ItWIduVRnzN5+NH+V34r8aW6GGi/UpeSXdCdl/hnJhuHa0BNVMg96GF1+INn11Eaka 2e5Zx9bsGEILUZSyDftjjIEcOP/ggxN1bac6wng1opvQnA2r9KKywfPgFHjy12/eE6ul njWA== X-Gm-Message-State: AOAM5316Zfxu77cLKFUVCrSk7tsFEGQAJbxMe8L2dvtCl/o1893uMwrF XFatyMDFv9ncazfLCGn/7gI= X-Google-Smtp-Source: ABdhPJzMcESu5Cbx/Bm26PisXXb7ZZwoEnDbyx0Z2S+ITP+5j3TnYCXDCPVUJswl8ArWoRKXLmmuoQ== X-Received: by 2002:aa7:c256:: with SMTP id y22mr6475707edo.324.1602694930983; Wed, 14 Oct 2020 10:02:10 -0700 (PDT) Received: from neptune.lab ([46.39.229.194]) by smtp.googlemail.com with ESMTPSA id g3sm76012edy.12.2020.10.14.10.02.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2020 10:02:10 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH 1/5] [RISCV_PM] Add J-extension into RISC-V Date: Wed, 14 Oct 2020 20:01:55 +0300 Message-Id: <20201014170159.26932-2-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201014170159.26932-1-space.monkey.delivers@gmail.com> References: <20201014170159.26932-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::542; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , "open list:All patches CC here" , space.monkey.delivers@gmail.com, Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..fe6bab4a52 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_j) { + target_misa |= RVJ; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -516,6 +519,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de275782e6..eca611a367 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -277,6 +278,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_counters; bool ext_ifencei; From patchwork Wed Oct 14 17:01:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 1382264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=nFT1oXhS; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CBJdG671Fz9sVJ for ; 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Wed, 14 Oct 2020 10:02:13 -0700 (PDT) Received: from neptune.lab ([46.39.229.194]) by smtp.googlemail.com with ESMTPSA id g3sm76012edy.12.2020.10.14.10.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2020 10:02:13 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Date: Wed, 14 Oct 2020 20:01:56 +0300 Message-Id: <20201014170159.26932-3-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201014170159.26932-1-space.monkey.delivers@gmail.com> References: <20201014170159.26932-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x630.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , "open list:All patches CC here" , space.monkey.delivers@gmail.com, Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 11 ++ target/riscv/cpu_bits.h | 66 +++++++++ target/riscv/csr.c | 302 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 380 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe6bab4a52..d63031eb08 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -440,6 +440,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.ext_j) { target_misa |= RVJ; + env->mmte |= PM_EXT_INITIAL; } if (cpu->cfg.ext_v) { target_misa |= RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eca611a367..21e47b8283 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -226,6 +226,17 @@ struct CPURISCVState { /* True if in debugger mode. */ bool debugger; + + /* CSRs for PM + * TODO: move these csr to appropriate groups + */ + target_ulong mmte; + target_ulong mpmmask; + target_ulong mpmbase; + target_ulong spmmask; + target_ulong spmbase; + target_ulong upmmask; + target_ulong upmbase; #endif float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..84c93c77ae 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -354,6 +354,21 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f +/* Custom user register */ +#define CSR_UMTE 0x8c0 +#define CSR_UPMMASK 0x8c1 +#define CSR_UPMBASE 0x8c2 + +/* Custom machine register */ +#define CSR_MMTE 0x7c0 +#define CSR_MPMMASK 0x7c1 +#define CSR_MPMBASE 0x7c2 + +/* Custom supervisor register */ +#define CSR_SMTE 0x9c0 +#define CSR_SPMMASK 0x9c1 +#define CSR_SPMBASE 0x9c2 + /* Legacy Machine Protection and Translation (priv v1.9.1) */ #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 @@ -604,4 +619,55 @@ #define MIE_UTIE (1 << IRQ_U_TIMER) #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) + +/* general mte CSR bits*/ +#define PM_ENABLE 0x00000001ULL +#define PM_CURRENT 0x00000002ULL +#define PM_XS_MASK 0x00000003ULL + +/* PM XS bits values */ +#define PM_EXT_DISABLE 0x00000000ULL +#define PM_EXT_INITIAL 0x00000001ULL +#define PM_EXT_CLEAN 0x00000002ULL +#define PM_EXT_DIRTY 0x00000003ULL + +/* offsets for every pair of control bits per each priv level */ +#define XS_OFFSET 0ULL +#define U_OFFSET 2ULL +#define S_OFFSET 4ULL +#define M_OFFSET 6ULL + +#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) +#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) +#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) +#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) +#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) +#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) + +/* mmte CSR bits */ +#define MMTE_PM_XS_BITS PM_XS_BITS +#define MMTE_U_PM_ENABLE U_PM_ENABLE +#define MMTE_U_PM_CURRENT U_PM_CURRENT +#define MMTE_S_PM_ENABLE S_PM_ENABLE +#define MMTE_S_PM_CURRENT S_PM_CURRENT +#define MMTE_M_PM_ENABLE M_PM_ENABLE +#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \ + MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \ + MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS) + +/* smte CSR bits */ +#define SMTE_PM_XS_BITS PM_XS_BITS +#define SMTE_U_PM_ENABLE U_PM_ENABLE +#define SMTE_U_PM_CURRENT U_PM_CURRENT +#define SMTE_S_PM_ENABLE S_PM_ENABLE +#define SMTE_S_PM_CURRENT S_PM_CURRENT +#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \ + SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \ + SMTE_PM_XS_BITS) + +/* umte CSR bits */ +#define UMTE_U_PM_ENABLE U_PM_ENABLE +#define UMTE_U_PM_CURRENT U_PM_CURRENT +#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT) + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..bbfbe71656 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -140,6 +140,11 @@ static int any(CPURISCVState *env, int csrno) return 0; } +static int umode(CPURISCVState *env, int csrno) +{ + return -!riscv_has_ext(env, RVU); +} + static int smode(CPURISCVState *env, int csrno) { return -!riscv_has_ext(env, RVS); @@ -1250,6 +1255,288 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) return 0; } +/* Functions to access Pointer Masking feature registers + * We have to check if current priv lvl could modify + * csr in given mode + */ +static int check_pm_current_disabled(CPURISCVState *env, int csrno) +{ + /* m-mode is always allowed to modify registers, so allow */ + if (env->priv == PRV_M) { + return 0; + } + int csr_priv = get_field(csrno, 0xC00); + /* If priv lvls differ that means we're accessing csr from higher priv lvl, so allow */ + if (env->priv != csr_priv) { + return 0; + } + int cur_bit_pos = (env->priv == PRV_U) ? U_PM_CURRENT : + (env->priv == PRV_S) ? S_PM_CURRENT : -1; + assert(cur_bit_pos != -1); + int pm_current = get_field(env->mmte, cur_bit_pos); + /* We're in same priv lvl, so we allow to modify csr only if pm_current==1 */ + return !pm_current; +} + +static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } +#endif + *val = env->mmte & MMTE_MASK; + return 0; +} + +static int write_mmte(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + target_ulong wpri_val = val & MMTE_MASK; + assert(val == wpri_val); + /* flush translation cache */ + if (val != env->mmte) { + tb_flush(env_cpu(env)); + } + env->mmte = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_smte(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } +#endif + *val = env->mmte & SMTE_MASK; + return 0; +} + +static int write_smte(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + target_ulong wpri_val = val & SMTE_MASK; + assert(val == wpri_val); + if (check_pm_current_disabled(env, csrno)) + return 0; + target_ulong new_val = val | (env->mmte & ~SMTE_MASK); + write_mmte(env, csrno, new_val); + return 0; +} + +static int read_umte(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } +#endif + *val = env->mmte & UMTE_MASK; + return 0; +} + +static int write_umte(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + target_ulong wpri_val = val & UMTE_MASK; + assert(val == wpri_val); + if (check_pm_current_disabled(env, csrno)) + return 0; + target_ulong new_val = val | (env->mmte & ~UMTE_MASK); + write_mmte(env, csrno, new_val); + return 0; +} + +static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->mpmmask; + return 0; +} + +static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (val != env->mpmmask) { + tb_flush(env_cpu(env)); + } + env->mpmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->spmmask; + return 0; +} + +static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + if (val != env->spmmask) { + tb_flush(env_cpu(env)); + } + env->spmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->upmmask; + return 0; +} + +static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + if (val != env->upmmask) { + tb_flush(env_cpu(env)); + } + env->upmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->mpmbase; + return 0; +} + +static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + /* flush translation cache */ + if (val != env->mpmbase) { + tb_flush(env_cpu(env)); + } + env->mpmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->spmbase; + return 0; +} + +static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + /* flush translation cache */ + if (val != env->spmbase) { + tb_flush(env_cpu(env)); + } + env->spmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->upmbase; + return 0; +} + +static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + /* flush translation cache */ + if (val != env->upmbase) { + tb_flush(env_cpu(env)); + } + env->upmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} #endif /* @@ -1471,6 +1758,21 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, + /* User Pointer Masking */ + [CSR_UMTE] = { umode, read_umte, write_umte }, + [CSR_UPMMASK] = { umode, read_upmmask, write_upmmask }, + [CSR_UPMBASE] = { umode, read_upmbase, write_upmbase }, + + /* Machine Pointer Masking */ + [CSR_MMTE] = { any, read_mmte, write_mmte }, + [CSR_MPMMASK] = { any, read_mpmmask, write_mpmmask }, + [CSR_MPMBASE] = { any, read_mpmbase, write_mpmbase }, + + /* Supervisor Pointer Masking */ + [CSR_SMTE] = { smode, read_smte, write_smte }, + [CSR_SPMMASK] = { smode, read_spmmask, write_spmmask }, + [CSR_SPMBASE] = { smode, read_spmbase, write_spmbase }, + /* Performance Counters */ [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, From patchwork Wed Oct 14 17:01:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 1382263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=RPOuWlFv; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CBJdG6043z9sTK for ; Thu, 15 Oct 2020 04:02:56 +1100 (AEDT) Received: from localhost ([::1]:37696 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kSkAt-0002sT-CK for incoming@patchwork.ozlabs.org; Wed, 14 Oct 2020 13:02:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kSkAN-0002p1-Qm; Wed, 14 Oct 2020 13:02:19 -0400 Received: from mail-ed1-x542.google.com ([2a00:1450:4864:20::542]:39837) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kSkAM-0000o6-3g; Wed, 14 Oct 2020 13:02:19 -0400 Received: by mail-ed1-x542.google.com with SMTP id t21so200612eds.6; Wed, 14 Oct 2020 10:02:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tA7JLmbIGrMajlGrZYwx7GZKaUy1dj+5f9/DC1Anv+U=; b=RPOuWlFvs0O9CT/MXSh+IPQtZeSBMjH7H2uZ1NmHoHDla2pm/LfYkKynw5b5KeetMy y8xAmZ0k95JicZTonxtnE3JgbtgpMAHM8cvPZOtFNKa0A1H53kp4+BCBjTz5AfB4qhSj MkuGQ74VXdTxDVzdB4jeXxUaw+6ar5GdEFOEO7T7aIJic8a0ELFcHAl6U7l1ZAnV4G5c 3oJddOnwyMCo8YbXeFu5WuXztw/yaN1ecCtPRjIYiRlbSTW7IPacw2/Nl3AkYJCqCnmj Ew9IF7Q8bBL5os8RbZlN4dNP5njK2Bn3Oxbg67TmQl7rU1BQuctWQU4h32ZUATbLpTua /Yxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tA7JLmbIGrMajlGrZYwx7GZKaUy1dj+5f9/DC1Anv+U=; b=Mn6+J8NcsSSiDbzxMTKx5x52jE0skD/84eJAzTZmmzYuxuSaLbhQupPkzBRSPk15K1 YyfDLErTPqz3BSgNFVw7Udb8LChHzb8iERx8E8qzWf8/DPusf45j7pK4v6zCxpDqqF0n 2hcM24UviJpzbAMTq9QrtddFFVCCyQPJpx02t0M3RBXRSPijjKPckyOOmV8EmoPBFC07 SlLmJpGOi3YNCdvEp7cSL33px+7iaTME1C1eb+q2a2gRt7gTJnYvkQNzSaz/AajxOXAD xJfb7AzbHVlThRNDIp2tDVZAHWqb49T09G7FTtUIGmDQwXo6Gx0dCa6CxAPNq+f426b+ QYlg== X-Gm-Message-State: AOAM5327105EF08hY29VpF/Km8JhYqqzMRrPefjfXtsa8ubPnqC8keeY wpE19eO1NPVqX5dvxqYRIDI= X-Google-Smtp-Source: ABdhPJwk9n524UEDD/4Qw/fVVfFqoT9SuRymQaDjAcyo4Dt0owTHKiHtTWclCHCO1k52mU9cg1tifg== X-Received: by 2002:a05:6402:b0e:: with SMTP id bm14mr6223869edb.19.1602694936452; Wed, 14 Oct 2020 10:02:16 -0700 (PDT) Received: from neptune.lab ([46.39.229.194]) by smtp.googlemail.com with ESMTPSA id g3sm76012edy.12.2020.10.14.10.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2020 10:02:15 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs Date: Wed, 14 Oct 2020 20:01:57 +0300 Message-Id: <20201014170159.26932-4-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201014170159.26932-1-space.monkey.delivers@gmail.com> References: <20201014170159.26932-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::542; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , "open list:All patches CC here" , space.monkey.delivers@gmail.com, Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d63031eb08..8f8ee4d29c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -255,6 +255,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); } + if (riscv_has_ext(env, RVH)) { + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", env->upmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", env->spmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", env->mpmbase); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", env->upmmask); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", env->spmmask); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", env->mpmmask); + } #endif for (i = 0; i < 32; i++) { From patchwork Wed Oct 14 17:01:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 1382270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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Wed, 14 Oct 2020 10:02:19 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH 4/5] [RISCV_PM] Add address masking functions required for RISC-V Pointer Masking extension Date: Wed, 14 Oct 2020 20:01:58 +0300 Message-Id: <20201014170159.26932-5-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201014170159.26932-1-space.monkey.delivers@gmail.com> References: <20201014170159.26932-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x636.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , "open list:All patches CC here" , space.monkey.delivers@gmail.com, Alistair Francis , Anatoly Parshintsev , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Anatoly Parshintsev Signed-off-by: Anatoly Parshintsev --- target/riscv/translate.c | 65 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..338a967e0c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -63,6 +63,10 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + /* PointerMasking extension */ + uint8_t pm_enabled; + target_ulong pm_mask; + target_ulong pm_base; } DisasContext; #ifdef TARGET_RISCV64 @@ -90,6 +94,38 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa & ext; } +/* Generates address adjustment for PointerMasking */ +static void gen_pm_adjust_address(DisasContext *s, + TCGv_i64 dst, + TCGv_i64 src) +{ + if (s->pm_enabled == 0) { + /* Load unmodified address */ + tcg_gen_mov_i64(dst, src); + } else { + TCGv_i64 mask_neg = tcg_const_i64(~s->pm_mask); + TCGv_i64 base = tcg_const_i64(s->pm_base); + /* calculate (addr & ~mask) */ + TCGv res1 = tcg_temp_new(); + tcg_gen_and_tl(res1, mask_neg, src); + /* calculate (1) | (base) */ + TCGv res2 = tcg_temp_new(); + tcg_gen_or_tl(res2, res1, base); + /* move result to dst */ + tcg_gen_mov_i64(dst, res2); + /* free allocated temps */ + tcg_temp_free(res1); + tcg_temp_free(res2); + tcg_temp_free_i64(mask_neg); + tcg_temp_free_i64(base); + } +} + +static TCGv_i64 apply_pointer_masking(DisasContext *s, TCGv_i64 addr) +{ + gen_pm_adjust_address(s, addr, addr); + return addr; +} /* * RISC-V requires NaN-boxing of narrower width floating point values. * This applies when a 32-bit value is assigned to a 64-bit FP register. @@ -800,8 +836,36 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) } else { ctx->virt_enabled = false; } + if (riscv_has_ext(env, RVJ)) { + switch (env->priv) { + case PRV_U: + ctx->pm_enabled = get_field(env->mmte, UMTE_U_PM_ENABLE); + ctx->pm_mask = env->upmmask; + ctx->pm_base = env->upmbase; + break; + case PRV_S: + ctx->pm_enabled = get_field(env->mmte, SMTE_S_PM_ENABLE); + ctx->pm_mask = env->spmmask; + ctx->pm_base = env->spmbase; + break; + case PRV_M: + ctx->pm_enabled = get_field(env->mmte, MMTE_M_PM_ENABLE); + ctx->pm_mask = env->mpmmask; + ctx->pm_base = env->mpmbase; + break; + default: + assert(0 && "Unreachable"); + } + } else { + ctx->pm_enabled = 0; + ctx->pm_mask = 0; + ctx->pm_base = 0; + } #else ctx->virt_enabled = false; + ctx->pm_enabled = 0; + ctx->pm_mask = 0; + ctx->pm_base = 0; #endif ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ @@ -932,3 +996,4 @@ void riscv_translate_init(void) load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), "load_val"); } + From patchwork Wed Oct 14 17:01:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 1382269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 14 Oct 2020 10:02:24 -0700 (PDT) Received: from neptune.lab ([46.39.229.194]) by smtp.googlemail.com with ESMTPSA id g3sm76012edy.12.2020.10.14.10.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2020 10:02:23 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH 5/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Date: Wed, 14 Oct 2020 20:01:59 +0300 Message-Id: <20201014170159.26932-6-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201014170159.26932-1-space.monkey.delivers@gmail.com> References: <20201014170159.26932-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x629.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, GAPPY_SUBJECT=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , "open list:All patches CC here" , space.monkey.delivers@gmail.com, Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/insn_trans/trans_rva.c.inc | 9 +++++++++ target/riscv/insn_trans/trans_rvd.c.inc | 6 ++++++ target/riscv/insn_trans/trans_rvf.c.inc | 6 ++++++ target/riscv/insn_trans/trans_rvi.c.inc | 6 ++++++ target/riscv/translate.c | 12 ++++++++++++ 5 files changed, 39 insertions(+) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index be8a9f06dd..3bf2e82013 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -26,6 +26,9 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } + if (has_ext(ctx, RVJ)) { + src1 = apply_pointer_masking(ctx, src1); + } tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop); if (a->aq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -46,6 +49,9 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGLabel *l2 = gen_new_label(); gen_get_gpr(src1, a->rs1); + if (has_ext(ctx, RVJ)) { + src1 = apply_pointer_masking(ctx, src1); + } tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); gen_get_gpr(src2, a->rs2); @@ -91,6 +97,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, gen_get_gpr(src1, a->rs1); gen_get_gpr(src2, a->rs2); + if (has_ext(ctx, RVJ)) { + src1 = apply_pointer_masking(ctx, src1); + } (*func)(src2, src1, src2, ctx->mem_idx, mop); gen_set_gpr(a->rd, src2); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 4f832637fa..0391bb02be 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -25,6 +25,9 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ); @@ -40,6 +43,9 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 3dfec8211d..176bc992e1 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,6 +30,9 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) TCGv t0 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); @@ -47,6 +50,9 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index d04ca0394c..3ee2fea271 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -141,6 +141,9 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) TCGv t1 = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); gen_set_gpr(a->rd, t1); @@ -180,6 +183,9 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) TCGv dat = tcg_temp_new(); gen_get_gpr(t0, a->rs1); tcg_gen_addi_tl(t0, t0, a->imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } gen_get_gpr(dat, a->rs2); tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 338a967e0c..0b086753d4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -416,6 +416,9 @@ static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, TCGv t1 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; if (memop < 0) { @@ -436,6 +439,9 @@ static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, TCGv dat = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + if (has_ext(ctx, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } gen_get_gpr(dat, rs2); int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; @@ -495,6 +501,9 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + if (riscv_has_ext(env, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } switch (opc) { case OPC_RISC_FLW: @@ -534,6 +543,9 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); tcg_gen_addi_tl(t0, t0, imm); + if (riscv_has_ext(env, RVJ)) { + t0 = apply_pointer_masking(ctx, t0); + } switch (opc) { case OPC_RISC_FSW: