From patchwork Fri Jan 10 08:12:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1220872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vG2p6sS9z9sRK for ; Fri, 10 Jan 2020 19:13:36 +1100 (AEDT) Received: from localhost ([::1]:42380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippQD-00030T-Ae for incoming@patchwork.ozlabs.org; Fri, 10 Jan 2020 03:13:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45716) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippPs-0002yp-AG for qemu-devel@nongnu.org; Fri, 10 Jan 2020 03:13:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ippPq-0004UU-Sw for qemu-devel@nongnu.org; Fri, 10 Jan 2020 03:13:12 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:49220) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ippPq-0003xX-H2; Fri, 10 Jan 2020 03:13:10 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08015814|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.380576-0.0141733-0.605251; DS=CONTINUE|ham_system_inform|0.0907534-0.000993834-0.908253; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03306; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GZbTVKh_1578643981; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GZbTVKh_1578643981) by smtp.aliyun-inc.com(10.147.41.158); Fri, 10 Jan 2020 16:13:01 +0800 From: LIU Zhiwei To: Alistair.Francis@wdc.com, palmer@dabbelt.com, chihmin.chao@sifive.com, jimw@sifive.com, bmeng.cn@gmail.com Subject: [PATCH 1/3] select gdb fpu xml by single or double float extension Date: Fri, 10 Jan 2020 16:12:18 +0800 Message-Id: <20200110081220.891-1-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" There is no reason why RISCV32 can't use RVD extension, or RISCV64 can't just use RVF extension. And gdb will check flen according to RVD or RVF feature in elf header. Signed-off-by: LIU Zhiwei --- configure | 4 ++-- target/riscv/gdbstub.c | 14 ++++++-------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/configure b/configure index 0ce2c0354a..2757c0a5a5 100755 --- a/configure +++ b/configure @@ -7679,13 +7679,13 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; sh4|sh4eb) TARGET_ARCH=sh4 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1a7947e019..e3c9b320fb 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -403,23 +403,21 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; -#if defined(TARGET_RISCV32) - if (env->misa & RVF) { + if (env->misa & RVD) { + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 36, "riscv-64bit-fpu.xml", 0); + } else if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-32bit-fpu.xml", 0); + 36, "riscv-32bit-fpu.xml", 0); } +#if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-32bit-csr.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) - if (env->misa & RVF) { - gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 36, "riscv-64bit-fpu.xml", 0); - } - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-64bit-csr.xml", 0); From patchwork Fri Jan 10 08:12:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1220873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vG3p1czRz9sRK for ; Fri, 10 Jan 2020 19:14:30 +1100 (AEDT) Received: from localhost ([::1]:42392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippR6-0004HU-2u for incoming@patchwork.ozlabs.org; Fri, 10 Jan 2020 03:14:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45712) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippPs-0002yo-9S for qemu-devel@nongnu.org; Fri, 10 Jan 2020 03:13:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ippPq-0004Um-U7 for qemu-devel@nongnu.org; Fri, 10 Jan 2020 03:13:11 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:33090) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ippPq-00043J-Hi; Fri, 10 Jan 2020 03:13:10 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07460611|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.195573-0.0212168-0.78321; DS=CONTINUE|ham_alarm|0.0142393-0.000318846-0.985442; FP=0|0|0|0|0|-1|-1|-1; HT=e01l04364; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GZbTVKh_1578643981; Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GZbTVKh_1578643981) by smtp.aliyun-inc.com(10.147.41.158); Fri, 10 Jan 2020 16:13:02 +0800 From: LIU Zhiwei To: Alistair.Francis@wdc.com, palmer@dabbelt.com, chihmin.chao@sifive.com, jimw@sifive.com, bmeng.cn@gmail.com Subject: [PATCH 2/3] RISC-V: use FIELD macro to define tb flags Date: Fri, 10 Jan 2020 16:12:19 +0800 Message-Id: <20200110081220.891-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200110081220.891-1-zhiwei_liu@c-sky.com> References: <20200110081220.891-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" FIELD is more unified to define tb flags. It is easier to add new filed to tb flags. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 15 +++++++++------ target/riscv/translate.c | 5 +++-- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e59343e13c..8efd4c5904 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -282,22 +282,25 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_MSTATUS_FS MSTATUS_FS +FIELD(TB_FLAGS, MMU, 0, 2) +FIELD(TB_FLAGS, FS, 13, 2) static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) + target_ulong *cs_base, uint32_t *pflags) { + uint32_t flags = 0; *pc = env->pc; *cs_base = 0; + #ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_MSTATUS_FS; + flags = FIELD_DP32(flags, TB_FLAGS, FS, MSTATUS_FS); #else - *flags = cpu_mmu_index(env, 0); + flags = FIELD_DP32(flags, TB_FLAGS, MMU, cpu_mmu_index(env, 0)); if (riscv_cpu_fp_enabled(env)) { - *flags |= TB_FLAGS_MSTATUS_FS; + flags = FIELD_DP32(flags, TB_FLAGS, FS, (env->mstatus & MSTATUS_FS)); } #endif + *pflags = flags; } int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ab6a891dc3..5de2d11d5c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -735,10 +735,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cs->env_ptr; RISCVCPU *cpu = RISCV_CPU(cs); + uint32_t tb_flags = ctx->base.tb->flags; ctx->pc_succ_insn = ctx->base.pc_first; - ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; - ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; + ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MMU); + ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); ctx->priv_ver = env->priv_ver; ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ From patchwork Fri Jan 10 08:12:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 1220878 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=c-sky.com Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47vG5T0r6Mz9sRQ for ; Fri, 10 Jan 2020 19:15:57 +1100 (AEDT) Received: from localhost ([::1]:42408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ippSU-0005OX-SW for incoming@patchwork.ozlabs.org; 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Fri, 10 Jan 2020 16:13:03 +0800 From: LIU Zhiwei To: Alistair.Francis@wdc.com, palmer@dabbelt.com, chihmin.chao@sifive.com, jimw@sifive.com, bmeng.cn@gmail.com Subject: [PATCH 3/3] remove redundant check for fpu csr read and write interface Date: Fri, 10 Jan 2020 16:12:20 +0800 Message-Id: <20200110081220.891-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200110081220.891-1-zhiwei_liu@c-sky.com> References: <20200110081220.891-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The read or write interface must be called after the predicate fs return 0. And the predicate will check (!env->debugger && !riscv_cpu_fp_enabled(env)), S0 no need to check again. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/csr.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index da02f9f0b1..0c2b8fc8f6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -107,11 +107,6 @@ static int pmp(CPURISCVState *env, int csrno) /* User Floating-Point CSRs */ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; - } -#endif *val = riscv_cpu_get_fflags(env); return 0; } @@ -119,9 +114,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; - } env->mstatus |= MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); @@ -130,11 +122,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; - } -#endif *val = env->frm; return 0; } @@ -142,9 +129,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; - } env->mstatus |= MSTATUS_FS; #endif env->frm = val & (FSR_RD >> FSR_RD_SHIFT); @@ -153,11 +137,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; - } -#endif *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); return 0; @@ -166,9 +145,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; - } env->mstatus |= MSTATUS_FS; #endif env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;