From patchwork Thu Oct 10 11:58:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1174505 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pqyv0Yxpz9sPd for ; Thu, 10 Oct 2019 23:24:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pqyt4ZDHzDr7D for ; Thu, 10 Oct 2019 23:24:38 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pqPR1p8wzDr4d for ; Thu, 10 Oct 2019 22:59:07 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) by bilbo.ozlabs.org (Postfix) with ESMTP id 46pqPQ4MC0z8wVP for ; Thu, 10 Oct 2019 22:59:06 +1100 (AEDT) Received: by ozlabs.org (Postfix) id 46pqPQ20yRz9sPq; Thu, 10 Oct 2019 22:59:06 +1100 (AEDT) Delivered-To: linuxppc-dev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pqPP4QqBz9sPp for ; Thu, 10 Oct 2019 22:59:05 +1100 (AEDT) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9ABMxTR102536 for ; Thu, 10 Oct 2019 07:58:55 -0400 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2vj1wjmq87-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 10 Oct 2019 07:58:54 -0400 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 10 Oct 2019 12:58:53 +0100 Received: from b06cxnps4075.portsmouth.uk.ibm.com (9.149.109.197) by e06smtp05.uk.ibm.com (192.168.101.135) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 10 Oct 2019 12:58:51 +0100 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9ABwnLa37028028 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Oct 2019 11:58:49 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5C06942041; Thu, 10 Oct 2019 11:58:49 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7068B42047; Thu, 10 Oct 2019 11:58:47 +0000 (GMT) Received: from pratiks-thinkpad.ibmuc.com (unknown [9.199.37.96]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 10 Oct 2019 11:58:47 +0000 (GMT) From: Pratik Rajesh Sampat To: linuxppc-dev@ozlabs.org, linux-next@vger.kernel.org, mpe@ellerman.id.au, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com Subject: [PATCH v1 1/3] powerpc/powernv: Interface to define support and preference for a SPR Date: Thu, 10 Oct 2019 17:28:41 +0530 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010115843.22283-1-psampat@linux.ibm.com> References: <20191010115843.22283-1-psampat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19101011-0020-0000-0000-00000377D897 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19101011-0021-0000-0000-000021CDE4A9 Message-Id: <20191010115843.22283-2-psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-10_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910100084 X-Mailman-Approved-At: Thu, 10 Oct 2019 23:17:34 +1100 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Define a bitmask interface to determine support for the Self Restore, Self Save or both. Also define an interface to determine the preference of that SPR to be strictly saved or restored or encapsulated with an order of preference. The preference bitmask is shown as below: ---------------------------- |... | 2nd pref | 1st pref | ---------------------------- MSB LSB The preference from higher to lower is from LSB to MSB with a shift of 8 bits. Example: Prefer self save first, if not available then prefer self restore The preference mask for this scenario will be seen as below. ((SELF_RESTORE_STRICT << PREFERENCE_SHIFT) | SELF_SAVE_STRICT) --------------------------------- |... | Self restore | Self save | --------------------------------- MSB LSB Finally, declare a list of preferred SPRs which encapsulate the bitmaks for preferred and supported with defaults of both being set to support legacy firmware. This commit also implements using the above interface and retains the legacy functionality of self restore. Signed-off-by: Pratik Rajesh Sampat --- arch/powerpc/platforms/powernv/idle.c | 284 +++++++++++++++++++++----- 1 file changed, 233 insertions(+), 51 deletions(-) diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c index 09f49eed7fb8..00b3fd58fafc 100644 --- a/arch/powerpc/platforms/powernv/idle.c +++ b/arch/powerpc/platforms/powernv/idle.c @@ -32,9 +32,100 @@ #define P9_STOP_SPR_MSR 2000 #define P9_STOP_SPR_PSSCR 855 +/* Interface for the stop state supported and preference */ +#define SELF_RESTORE_TYPE 0 +#define SELF_SAVE_TYPE 1 + +#define NR_PREFERENCES 2 +#define PREFERENCE_SHIFT 8 +#define PREFERENCE_MASK 0xff + +#define UNSUPPORTED 0x0 +#define SELF_RESTORE_STRICT 0x01 +#define SELF_SAVE_STRICT 0x10 + +/* + * Bitmask defining the kind of preferences available. + * Note : The higher to lower preference is from LSB to MSB, with a shift of + * 8 bits. + * ---------------------------- + * | | 2nd pref | 1st pref | + * ---------------------------- + * MSB LSB + */ +/* Prefer Restore if available, otherwise unsupported */ +#define PREFER_SELF_RESTORE_ONLY SELF_RESTORE_STRICT +/* Prefer Save if available, otherwise unsupported */ +#define PREFER_SELF_SAVE_ONLY SELF_SAVE_STRICT +/* Prefer Restore when available, otherwise prefer Save */ +#define PREFER_RESTORE_SAVE ((SELF_SAVE_STRICT << \ + PREFERENCE_SHIFT)\ + | SELF_RESTORE_STRICT) +/* Prefer Save when available, otherwise prefer Restore*/ +#define PREFER_SAVE_RESTORE ((SELF_RESTORE_STRICT <<\ + PREFERENCE_SHIFT)\ + | SELF_SAVE_STRICT) static u32 supported_cpuidle_states; struct pnv_idle_states_t *pnv_idle_states; int nr_pnv_idle_states; +/* Caching the lpcr support to use later */ +static bool is_lpcr_self_save; + +struct preferred_sprs { + u64 spr; + u32 preferred_mode; + u32 supported_mode; +}; + +struct preferred_sprs preferred_sprs[] = { + { + .spr = SPRN_HSPRG0, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = SPRN_LPCR, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = SPRN_HMEER, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = SPRN_HID0, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = P9_STOP_SPR_MSR, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = P9_STOP_SPR_PSSCR, + .preferred_mode = PREFER_SAVE_RESTORE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = SPRN_HID1, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = SPRN_HID4, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + }, + { + .spr = SPRN_HID5, + .preferred_mode = PREFER_RESTORE_SAVE, + .supported_mode = SELF_RESTORE_STRICT, + } +}; + +const int nr_preferred_sprs = ARRAY_SIZE(preferred_sprs); /* * The default stop state that will be used by ppc_md.power_save @@ -61,78 +152,166 @@ static bool deepest_stop_found; static unsigned long power7_offline_type; -static int pnv_save_sprs_for_deep_states(void) +static int pnv_self_restore_sprs(u64 pir, int cpu, u64 spr) { - int cpu; + u64 reg_val; int rc; - /* - * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across - * all cpus at boot. Get these reg values of current cpu and use the - * same across all cpus. - */ - uint64_t lpcr_val = mfspr(SPRN_LPCR); - uint64_t hid0_val = mfspr(SPRN_HID0); - uint64_t hid1_val = mfspr(SPRN_HID1); - uint64_t hid4_val = mfspr(SPRN_HID4); - uint64_t hid5_val = mfspr(SPRN_HID5); - uint64_t hmeer_val = mfspr(SPRN_HMEER); - uint64_t msr_val = MSR_IDLE; - uint64_t psscr_val = pnv_deepest_stop_psscr_val; - - for_each_present_cpu(cpu) { - uint64_t pir = get_hard_smp_processor_id(cpu); - uint64_t hsprg0_val = (uint64_t)paca_ptrs[cpu]; - - rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); + switch (spr) { + case SPRN_HSPRG0: + reg_val = (uint64_t)paca_ptrs[cpu]; + rc = opal_slw_set_reg(pir, SPRN_HSPRG0, reg_val); if (rc != 0) return rc; - - rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); + break; + case SPRN_LPCR: + reg_val = mfspr(SPRN_LPCR); + rc = opal_slw_set_reg(pir, SPRN_LPCR, reg_val); if (rc != 0) return rc; - + break; + case P9_STOP_SPR_MSR: + reg_val = MSR_IDLE; if (cpu_has_feature(CPU_FTR_ARCH_300)) { - rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); + rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, reg_val); if (rc) return rc; - - rc = opal_slw_set_reg(pir, - P9_STOP_SPR_PSSCR, psscr_val); - + } + break; + case P9_STOP_SPR_PSSCR: + reg_val = pnv_deepest_stop_psscr_val; + if (cpu_has_feature(CPU_FTR_ARCH_300)) { + rc = opal_slw_set_reg(pir, P9_STOP_SPR_PSSCR, reg_val); if (rc) return rc; } - - /* HIDs are per core registers */ + break; + case SPRN_HMEER: + reg_val = mfspr(SPRN_HMEER); if (cpu_thread_in_core(cpu) == 0) { - - rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); - if (rc != 0) + rc = opal_slw_set_reg(pir, SPRN_HMEER, reg_val); + if (rc) return rc; - - rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); - if (rc != 0) + } + break; + case SPRN_HID0: + reg_val = mfspr(SPRN_HID0); + if (cpu_thread_in_core(cpu) == 0) { + rc = opal_slw_set_reg(pir, SPRN_HID0, reg_val); + if (rc) + return rc; + } + break; + case SPRN_HID1: + reg_val = mfspr(SPRN_HID1); + if (cpu_thread_in_core(cpu) == 0 && + !cpu_has_feature(CPU_FTR_ARCH_300)) { + rc = opal_slw_set_reg(pir, SPRN_HID1, reg_val); + if (rc) return rc; + } + break; + case SPRN_HID4: + reg_val = mfspr(SPRN_HID4); + if (cpu_thread_in_core(cpu) == 0 && + !cpu_has_feature(CPU_FTR_ARCH_300)) { + rc = opal_slw_set_reg(pir, SPRN_HID4, reg_val); + if (rc) + return rc; + } + break; + case SPRN_HID5: + reg_val = mfspr(SPRN_HID5); + if (cpu_thread_in_core(cpu) == 0 && + !cpu_has_feature(CPU_FTR_ARCH_300)) { + rc = opal_slw_set_reg(pir, SPRN_HID5, reg_val); + if (rc) + return rc; + } + break; + default: + return -EINVAL; + } + return 0; +} - /* Only p8 needs to set extra HID regiters */ - if (!cpu_has_feature(CPU_FTR_ARCH_300)) { +static int pnv_self_save_restore_sprs(void) +{ + int rc, index, cpu, k; + u64 pir; + struct preferred_sprs curr_spr; + bool is_initialized; + u32 preferred; + is_lpcr_self_save = false; - rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); - if (rc != 0) - return rc; + for_each_present_cpu(cpu) { + pir = get_hard_smp_processor_id(cpu); + for (index = 0; index < nr_preferred_sprs; index++) { + curr_spr = preferred_sprs[index]; + is_initialized = false; + /* + * Go through each of the preferences + * Check if it is preferred as well as supported + */ + for (k = 0; k < NR_PREFERENCES; k++) { + preferred = curr_spr.preferred_mode + & PREFERENCE_MASK; + if (preferred & curr_spr.supported_mode + & SELF_RESTORE_STRICT) { + is_initialized = true; + rc = pnv_self_restore_sprs(pir, cpu, + curr_spr.spr); + if (rc != 0) + return rc; + break; + } + preferred_sprs[index].preferred_mode = + preferred_sprs[index].preferred_mode >> + PREFERENCE_SHIFT; + curr_spr = preferred_sprs[index]; + } + if (!is_initialized) { + if (cpu_has_feature(CPU_FTR_ARCH_300) && + (preferred_sprs[index].spr == SPRN_HID1 || + preferred_sprs[index].spr == SPRN_HID4 || + preferred_sprs[index].spr == SPRN_HID5)) + continue; + return OPAL_UNSUPPORTED; + } + } + } + return 0; +} - rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); - if (rc != 0) - return rc; +static int pnv_save_sprs_for_deep_states(void) +{ + int rc; + int index; - rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); - if (rc != 0) - return rc; - } + /* + * Iterate over the preffered SPRs and if even one of them is + * still unsupported We cut support for deep stop states + */ + for (index = 0; index < nr_preferred_sprs; index++) { + if (preferred_sprs[index].supported_mode == UNSUPPORTED) { + if (cpu_has_feature(CPU_FTR_ARCH_300) && + (preferred_sprs[index].spr == SPRN_HID1 || + preferred_sprs[index].spr == SPRN_HID4 || + preferred_sprs[index].spr == SPRN_HID5)) + continue; + return OPAL_UNSUPPORTED; } } + /* + * Try to self-restore the registers that can be self restored if self + * restore is active, try the same for the registers that + * can be self saved too. + * Note : If both are supported, self restore is given more priority + */ + rc = pnv_self_save_restore_sprs(); + if (rc != 0) + return rc; return 0; } @@ -954,8 +1133,11 @@ void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val) * Program the LPCR via stop-api only if the deepest stop state * can lose hypervisor context. */ - if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) - opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); + if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) { + if (!is_lpcr_self_save) + opal_slw_set_reg(pir, SPRN_LPCR, + lpcr_val); + } } /* From patchwork Thu Oct 10 11:58:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1174510 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pr2z6bX3z9sPJ for ; Thu, 10 Oct 2019 23:28:11 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pr2z1vffzDqmT for ; Thu, 10 Oct 2019 23:28:11 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pqPR1lhYzDr4Q for ; Thu, 10 Oct 2019 22:59:07 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id 46pqPQ4FQ2z8tL0 for ; Thu, 10 Oct 2019 22:59:06 +1100 (AEDT) Received: by ozlabs.org (Postfix) id 46pqPQ233Dz9sPw; Thu, 10 Oct 2019 22:59:06 +1100 (AEDT) Delivered-To: linuxppc-dev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pqPP4QpQz9sPk for ; Thu, 10 Oct 2019 22:59:05 +1100 (AEDT) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9AB53RK102409 for ; Thu, 10 Oct 2019 07:58:56 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0b-001b2d01.pphosted.com with ESMTP id 2vj1nawc0r-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 10 Oct 2019 07:58:56 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 10 Oct 2019 12:58:54 +0100 Received: from b06avi18878370.portsmouth.uk.ibm.com (9.149.26.194) by e06smtp03.uk.ibm.com (192.168.101.133) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 10 Oct 2019 12:58:53 +0100 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9ABwpVg44040616 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Oct 2019 11:58:51 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89BCF4204B; Thu, 10 Oct 2019 11:58:51 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C6F8342047; Thu, 10 Oct 2019 11:58:49 +0000 (GMT) Received: from pratiks-thinkpad.ibmuc.com (unknown [9.199.37.96]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 10 Oct 2019 11:58:49 +0000 (GMT) From: Pratik Rajesh Sampat To: linuxppc-dev@ozlabs.org, linux-next@vger.kernel.org, mpe@ellerman.id.au, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com Subject: [PATCH v1 2/3] powerpc/powernv: Introduce Self save support Date: Thu, 10 Oct 2019 17:28:42 +0530 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010115843.22283-1-psampat@linux.ibm.com> References: <20191010115843.22283-1-psampat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19101011-0012-0000-0000-00000356DAE3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19101011-0013-0000-0000-00002191E3B1 Message-Id: <20191010115843.22283-3-psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-10_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910100084 X-Mailman-Approved-At: Thu, 10 Oct 2019 23:17:34 +1100 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This commit introduces and leverages the Self save API which OPAL now supports. Add the new Self Save OPAL API call in the list of OPAL calls. Implement the self saving of the SPRs based on the support populated while respecting it's preferences. This implementation allows mixing of support for the SPRs, which means that a SPR can be self restored while another SPR be self saved if they support and prefer it to be so. Signed-off-by: Pratik Rajesh Sampat --- arch/powerpc/include/asm/opal-api.h | 3 ++- arch/powerpc/include/asm/opal.h | 1 + arch/powerpc/platforms/powernv/idle.c | 16 ++++++++++++++++ arch/powerpc/platforms/powernv/opal-call.c | 1 + 4 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h index 383242eb0dea..4ee1641c60a4 100644 --- a/arch/powerpc/include/asm/opal-api.h +++ b/arch/powerpc/include/asm/opal-api.h @@ -208,7 +208,8 @@ #define OPAL_HANDLE_HMI2 166 #define OPAL_NX_COPROC_INIT 167 #define OPAL_XIVE_GET_VP_STATE 170 -#define OPAL_LAST 170 +#define OPAL_SLW_SELF_SAVE_REG 173 +#define OPAL_LAST 173 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h index 57bd029c715e..832eff21d189 100644 --- a/arch/powerpc/include/asm/opal.h +++ b/arch/powerpc/include/asm/opal.h @@ -202,6 +202,7 @@ int64_t opal_handle_hmi(void); int64_t opal_handle_hmi2(__be64 *out_flags); int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end); int64_t opal_unregister_dump_region(uint32_t id); +int64_t opal_slw_self_save_reg(uint64_t cpu_pir, uint64_t sprn); int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag); int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number); diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c index 00b3fd58fafc..f0dd377820c7 100644 --- a/arch/powerpc/platforms/powernv/idle.c +++ b/arch/powerpc/platforms/powernv/idle.c @@ -264,6 +264,20 @@ static int pnv_self_save_restore_sprs(void) if (rc != 0) return rc; break; + } else if (preferred & curr_spr.supported_mode + & SELF_SAVE_STRICT) { + is_initialized = true; + if (curr_spr.spr == SPRN_HMEER && + cpu_thread_in_core(cpu) != 0) { + continue; + } + if (curr_spr.spr == SPRN_LPCR) + is_lpcr_self_save = true; + rc = opal_slw_self_save_reg(pir, + curr_spr.spr); + if (rc != 0) + return rc; + break; } preferred_sprs[index].preferred_mode = preferred_sprs[index].preferred_mode >> @@ -1137,6 +1151,8 @@ void pnv_program_cpu_hotplug_lpcr(unsigned int cpu, u64 lpcr_val) if (!is_lpcr_self_save) opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); + else + opal_slw_self_save_reg(pir, SPRN_LPCR); } } diff --git a/arch/powerpc/platforms/powernv/opal-call.c b/arch/powerpc/platforms/powernv/opal-call.c index 29ca523c1c79..716f2118939b 100644 --- a/arch/powerpc/platforms/powernv/opal-call.c +++ b/arch/powerpc/platforms/powernv/opal-call.c @@ -223,6 +223,7 @@ OPAL_CALL(opal_handle_hmi, OPAL_HANDLE_HMI); OPAL_CALL(opal_handle_hmi2, OPAL_HANDLE_HMI2); OPAL_CALL(opal_config_cpu_idle_state, OPAL_CONFIG_CPU_IDLE_STATE); OPAL_CALL(opal_slw_set_reg, OPAL_SLW_SET_REG); +OPAL_CALL(opal_slw_self_save_reg, OPAL_SLW_SELF_SAVE_REG); OPAL_CALL(opal_register_dump_region, OPAL_REGISTER_DUMP_REGION); OPAL_CALL(opal_unregister_dump_region, OPAL_UNREGISTER_DUMP_REGION); OPAL_CALL(opal_pci_set_phb_cxl_mode, OPAL_PCI_SET_PHB_CAPI_MODE); From patchwork Thu Oct 10 11:58:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1174513 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pr67090Wz9sCJ for ; Thu, 10 Oct 2019 23:30:55 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46pr664hPyzDr6D for ; Thu, 10 Oct 2019 23:30:54 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pqPS5ZQTzDr4Q for ; Thu, 10 Oct 2019 22:59:08 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from ozlabs.org (bilbo.ozlabs.org [203.11.71.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id 46pqPR1bNgz8x4q for ; Thu, 10 Oct 2019 22:59:07 +1100 (AEDT) Received: by ozlabs.org (Postfix) id 46pqPQ6vn1z9sPk; Thu, 10 Oct 2019 22:59:06 +1100 (AEDT) Delivered-To: linuxppc-dev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pqPQ18mNz9sPL for ; Thu, 10 Oct 2019 22:59:05 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9AAqG1K196426 for ; Thu, 10 Oct 2019 07:58:59 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2vj38yhvkx-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 10 Oct 2019 07:58:58 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 10 Oct 2019 12:58:57 +0100 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp01.uk.ibm.com (192.168.101.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 10 Oct 2019 12:58:55 +0100 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9ABwrpc41156610 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Oct 2019 11:58:54 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C6B474204C; Thu, 10 Oct 2019 11:58:53 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DD4A442049; Thu, 10 Oct 2019 11:58:51 +0000 (GMT) Received: from pratiks-thinkpad.ibmuc.com (unknown [9.199.37.96]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 10 Oct 2019 11:58:51 +0000 (GMT) From: Pratik Rajesh Sampat To: linuxppc-dev@ozlabs.org, linux-next@vger.kernel.org, mpe@ellerman.id.au, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com Subject: [PATCH v1 3/3] powerpc/powernv: Parse device tree, population of SPR support Date: Thu, 10 Oct 2019 17:28:43 +0530 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010115843.22283-1-psampat@linux.ibm.com> References: <20191010115843.22283-1-psampat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19101011-4275-0000-0000-00000370DB11 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19101011-4276-0000-0000-00003883E27B Message-Id: <20191010115843.22283-4-psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-10_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910100084 X-Mailman-Approved-At: Thu, 10 Oct 2019 23:17:34 +1100 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Parse the device tree for nodes self-save, self-restore and populate support for the preferred SPRs based what was advertised by the device tree. Signed-off-by: Pratik Rajesh Sampat --- arch/powerpc/platforms/powernv/idle.c | 104 ++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c index f0dd377820c7..43ad0e543b84 100644 --- a/arch/powerpc/platforms/powernv/idle.c +++ b/arch/powerpc/platforms/powernv/idle.c @@ -1408,6 +1408,107 @@ static void __init pnv_probe_idle_states(void) supported_cpuidle_states |= pnv_idle_states[i].flags; } +/* + * Extracts and populates the self save or restore capabilities + * passed from the device tree node + */ +static int extract_save_restore_state_dt(struct device_node *np, int type) +{ + int nr_sprns = 0, i, bitmask_index; + int rc = 0; + u32 active = 0; + u64 *temp_u64; + u64 bit_pos; + + if (of_property_read_u32(np, "active", &active)) { + pr_warn("opal: failed to find the active value for self save/restore node"); + return -EINVAL; + } + + if (!active) { + /* + * if the feature is not active, strip the preferred_sprs from + * that capability. + */ + if (type == SELF_RESTORE_TYPE) { + for (i = 0; i < nr_preferred_sprs; i++) { + preferred_sprs[i].supported_mode &= + ~SELF_RESTORE_STRICT; + } + } else { + for (i = 0; i < nr_preferred_sprs; i++) { + preferred_sprs[i].supported_mode &= + ~SELF_SAVE_STRICT; + } + } + return 0; + } + nr_sprns = of_property_count_u64_elems(np, "sprn-bitmask"); + if (nr_sprns <= 0) + return rc; + temp_u64 = kcalloc(nr_sprns, sizeof(u64), GFP_KERNEL); + if (of_property_read_u64_array(np, "sprn-bitmask", + temp_u64, nr_sprns)) { + pr_warn("cpuidle-powernv: failed to find registers in DT\n"); + kfree(temp_u64); + return -EINVAL; + } + /* + * Populate acknowledgment of support for the sprs in the global vector + * gotten by the registers supplied by the firmware. + * The registers are in a bitmask, bit index within + * that specifies the SPR + */ + for (i = 0; i < nr_preferred_sprs; i++) { + bitmask_index = preferred_sprs[i].spr / 64; + bit_pos = preferred_sprs[i].spr % 64; + if ((temp_u64[bitmask_index] & (1UL << bit_pos)) == 0) { + if (type == SELF_RESTORE_TYPE) + preferred_sprs[i].supported_mode &= + ~SELF_RESTORE_STRICT; + else + preferred_sprs[i].supported_mode &= + ~SELF_SAVE_STRICT; + continue; + } + if (type == SELF_RESTORE_TYPE) { + preferred_sprs[i].supported_mode |= + SELF_RESTORE_STRICT; + } else { + preferred_sprs[i].supported_mode |= + SELF_SAVE_STRICT; + } + } + + kfree(temp_u64); + return rc; +} + +static int pnv_parse_deepstate_dt(void) +{ + struct device_node *np, *np1; + int rc = 0; + + /* Self restore register population */ + np = of_find_node_by_path("/ibm,opal/power-mgt/self-restore"); + if (!np) { + pr_warn("opal: self restore Node not found"); + } else { + rc = extract_save_restore_state_dt(np, SELF_RESTORE_TYPE); + if (rc != 0) + return rc; + } + /* Self save register population */ + np1 = of_find_node_by_path("/ibm,opal/power-mgt/self-save"); + if (!np1) { + pr_warn("opal: self save Node not found"); + pr_warn("Legacy firmware. Assuming default self-restore support"); + } else { + rc = extract_save_restore_state_dt(np1, SELF_SAVE_TYPE); + } + return rc; +} + /* * This function parses device-tree and populates all the information * into pnv_idle_states structure. It also sets up nr_pnv_idle_states @@ -1556,6 +1657,9 @@ static int __init pnv_init_idle_states(void) return rc; pnv_probe_idle_states(); + rc = pnv_parse_deepstate_dt(); + if (rc) + return rc; if (!cpu_has_feature(CPU_FTR_ARCH_300)) { if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { power7_fastsleep_workaround_entry = false;