From patchwork Thu Nov 2 10:26:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Biao X-Patchwork-Id: 833274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ySLt61KXkz9t30 for ; Thu, 2 Nov 2017 21:29:08 +1100 (AEDT) Received: from localhost ([::1]:59537 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eACkE-0006MZ-Ac for incoming@patchwork.ozlabs.org; Thu, 02 Nov 2017 06:29:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eACju-0006MH-Ny for qemu-devel@nongnu.org; Thu, 02 Nov 2017 06:28:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eACjr-0000fh-L9 for qemu-devel@nongnu.org; Thu, 02 Nov 2017 06:28:46 -0400 Received: from mxhk.zte.com.cn ([63.217.80.70]:37572) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eACjr-0000YG-9m for qemu-devel@nongnu.org; Thu, 02 Nov 2017 06:28:43 -0400 Received: from mse01.zte.com.cn (unknown [10.30.3.20]) by Forcepoint Email with ESMTPS id B7DFE170C3AAC50FBE60; Thu, 2 Nov 2017 18:28:36 +0800 (CST) Received: from notes_smtp.zte.com.cn ([10.30.1.239]) by mse01.zte.com.cn with ESMTP id vA2ASPhh000327; Thu, 2 Nov 2017 18:28:25 +0800 (GMT-8) (envelope-from jiang.biao2@zte.com.cn) Received: from localhost.localdomain ([10.75.10.200]) by szsmtp06.zte.com.cn (Lotus Domino Release 8.5.3FP6) with ESMTP id 2017110218283070-392484 ; Thu, 2 Nov 2017 18:28:30 +0800 From: Jiang Biao To: aurelien@aurel32.net, rth@twiddle.net Date: Thu, 2 Nov 2017 18:26:15 +0800 Message-Id: <1509618375-164238-1-git-send-email-jiang.biao2@zte.com.cn> X-Mailer: git-send-email 1.8.3.1 X-MIMETrack: Itemize by SMTP Server on SZSMTP06/server/zte_ltd(Release 8.5.3FP6|November 21, 2013) at 2017-11-02 18:28:30, Serialize by Router on notes_smtp/zte_ltd(Release 9.0.1FP7|August 17, 2016) at 2017-11-02 18:28:14, Serialize complete at 2017-11-02 18:28:14 X-MAIL: mse01.zte.com.cn vA2ASPhh000327 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 63.217.80.70 Subject: [Qemu-devel] [PATCH] tcg/mips: make some functions inline. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jiang.biao2@zte.com.cn, zhong.weidong@zte.com.cn, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Make some functions inline. Signed-off-by: Jiang Biao --- tcg/mips/tcg-target.inc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 4b55ab8..f83a8ec 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -168,7 +168,7 @@ static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); } -static void patch_reloc(tcg_insn_unit *code_ptr, int type, +static inline void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { tcg_debug_assert(type == R_MIPS_PC16); @@ -507,7 +507,7 @@ static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, } -static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, +static inline void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, TCGReg rd, TCGReg rt, TCGArg sa) { int32_t inst; @@ -637,13 +637,13 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) } } -static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) +static inline void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) { bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); tcg_debug_assert(ok); } -static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) +static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); @@ -656,7 +656,7 @@ static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) } } -static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) +static inline void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); @@ -670,7 +670,7 @@ static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) } } -static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) +static inline void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); @@ -1103,7 +1103,7 @@ static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) } } -static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) { tcg_out_call_int(s, arg, false); tcg_out_nop(s); @@ -1661,7 +1661,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #endif } -static void tcg_out_mb(TCGContext *s, TCGArg a0) +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) { static const MIPSInsn sync[] = { /* Note that SYNC_MB is a slightly weaker than SYNC 0, @@ -2433,7 +2433,7 @@ static void tcg_target_detect_isa(void) sigaction(SIGILL, &sa_old, NULL); } -static tcg_insn_unit *align_code_ptr(TCGContext *s) +static inline tcg_insn_unit *align_code_ptr(TCGContext *s) { uintptr_t p = (uintptr_t)s->code_ptr; if (p & 15) {