From patchwork Sun Oct 29 10:13:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GDFT4es7"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtl13Vg7z9sxR for ; Sun, 29 Oct 2017 21:14:37 +1100 (AEDT) Received: from localhost ([::1]:35455 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbz-0006WL-GS for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:14:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbJ-0006UD-0z for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbG-0007oM-US for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:52 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:55084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbG-0007mx-N7 for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:50 -0400 Received: by mail-lf0-x243.google.com with SMTP id a2so11637261lfh.11 for ; Sun, 29 Oct 2017 03:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GSdtpuCvBiQtSQCI47CTW/6OXBGqcgpBOXFlYceeytI=; b=GDFT4es7xM5PHCxItEKISdLfFVyDNhpLo37t9ixzf5brbTNadCcyGFfE3+1CfyYJKZ 11GtmFlnC9DJYx5YtKxCFWFd2zAIyF7y1q6fPPpgTREKUwJ22U7uqfg0vqdcaqo4jgZn NNFfTSiBREu/MVrFThk5Lt1nltinjwa5SWEvpQmtzuw+IDKoX39T+pT9wi8qjehOZdWO 5DCa7VQvpGGurYq3qcqLcVpItUjfh6TIBC3GT5OeAgAPvpOx4AWlmuPays/etF7uqSMK WwH6g/zdKokmEY77oqm3xxGLU7AoW3yAI7Z1IMp4WbWwF07JWKhO+WsG4aLl6LbWIPb8 JVVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GSdtpuCvBiQtSQCI47CTW/6OXBGqcgpBOXFlYceeytI=; b=cUlXGaL/0CHZlXTEVFt4aTTdP9RKUbzhjwXTM15tAYgPgReAN5olp9N+DwLrVwUGk5 aKbPhOvg8Sg28cSt1m7puZLW+qJbi1I9HuGb11WSMrvVU3eU2wn2HuSMg/Dy3ptS61MS xl7OuA0UoVkZNE+2Gpn/0zlmguO0r+Z9Sw2EMChh7izHj9SHGPqab/l/Rm+3XvRTpiWg CewNhlXd6xuX80kHzF4GYLT3+gqJQuno1F5OKqckrubk9iuXPFF8CkFln/yDwtyeSGWa HMVKPL/hZW7FcITeGv+dUt3BfZRiKtWdFM/RDgObRXW2HnbsAi3aV/PPom18jXa4uA65 u8xA== X-Gm-Message-State: AMCzsaXscczyXEj81VQhIC1G7SEf1d67Q+UcgKq6wNmZ20Wu55uZZNjy kBLXSczoZpLhhont0Hqvei64KQ== X-Google-Smtp-Source: ABhQp+Rn7zXUKVbA44+MvGpXaeWb74Wsrrx46F7HMmroprKJTz2o8vYLoioM7ldpMzy7vBgcVPFtsA== X-Received: by 10.25.90.81 with SMTP id o78mr1763435lfb.80.1509272029191; Sun, 29 Oct 2017 03:13:49 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:48 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:31 +0100 Message-Id: <20171029101343.15544-2-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v5 01/13] m25p80: Add support for continuous read out of RDSR and READ_FSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. This feature is supported by amongst others 1 or more flashtypes manufactured by Numonyx (Micron), Windbond, SST, Gigadevice, Eon and Macronix. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemiński Acked-by: Alistair Francis --- hw/block/m25p80.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index a2438b9..2971519 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -423,6 +423,7 @@ typedef struct Flash { uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; uint32_t len; uint32_t pos; + bool data_read_loop; uint8_t needed_bytes; uint8_t cmd_in_progress; uint32_t cur_addr; @@ -983,6 +984,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos = 0; s->len = 1; + s->data_read_loop = true; s->state = STATE_READING_DATA; break; @@ -993,6 +995,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos = 0; s->len = 1; + s->data_read_loop = true; s->state = STATE_READING_DATA; break; @@ -1133,6 +1136,7 @@ static int m25p80_cs(SSISlave *ss, bool select) s->pos = 0; s->state = STATE_IDLE; flash_sync_dirty(s, -1); + s->data_read_loop = false; } DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); @@ -1198,7 +1202,9 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) s->pos++; if (s->pos == s->len) { s->pos = 0; - s->state = STATE_IDLE; + if (!s->data_read_loop) { + s->state = STATE_IDLE; + } } break; From patchwork Sun Oct 29 10:13:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831703 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Nhjn0NtE"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtpJ6wDZz9t0F for ; Sun, 29 Oct 2017 21:17:28 +1100 (AEDT) Received: from localhost ([::1]:35469 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kek-0000PJ-UB for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:17:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbJ-0006UE-7F for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbI-0007pN-93 for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:53 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:56413) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbI-0007oZ-1Q for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:52 -0400 Received: by mail-lf0-x244.google.com with SMTP id 90so11649040lfs.13 for ; Sun, 29 Oct 2017 03:13:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LQ0ruKnUlE+DgyjYfHiKoTnB/n7tJczzW3/L1uLzZ+w=; b=Nhjn0NtEEN5UE9f0qlLRMDu6tXcrYzCFuw8oWv0C9CUaqETGFL8rGei0lGu5mlWagN MhobOXfvR05tpigVtI29R3JzUCPgiMEImGVRHULgWWTsz2hQQ2oghjHXXcd89+LNBF0s Li4t28sEwNpHbtclmSTe9elKYX/39ox3PHGpBI++io1hF3Q06afq+3mgxzkXbA/4f6iL hNOTyQCvbS019cuBbZ6vCSbuZWV6Td1GRurJajg0uTsRGrjMsxgRXmSA0dqNwNHGJpDD 6Gu/EWR073Dnc/bhJ4L/KSzKmaiFn4FoaVmECdVkQbZeVSvuMP8ZNkZlPN4J4zXuuGBC xZag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LQ0ruKnUlE+DgyjYfHiKoTnB/n7tJczzW3/L1uLzZ+w=; b=aKqQ7yFQoO8Dp8L46KTyuxXtRKWvZkFlDheh4qzJWdj+cZvu5CATG0N9TfZt8wBFqi V8xitAbTFrga33kq0Tc8iMYnMpvNiAK5u7QOuAquY4X+8T4QnMdJudCt6z/Yljgdqvyn +pKtdqH57o7DfDSM8MEKJwxFn99i9M6k5VDCp4hxzkj8jWMORAZMpZy+4mdWhkBBYewC KRVvsdmKi3XP5ylo9vf5Sou5u+zDZ6YJrVSB2CGxF5wPxsWYhh/dIo+P5FyLpGzv66yT aXfqYJjHY4/uszhMgCpziVEgkR0ycyjOeat3oBtmsDeTRNwAortbssmx1uhGJhBekPcJ TMxA== X-Gm-Message-State: AMCzsaXgwf0ZlH3aRmKk9ks+YuKkIaHCKbLEeSK72QjllvLjxTqnn0R1 Ngx7r8aNV505O9oToIiIWqNmuA== X-Google-Smtp-Source: ABhQp+RXkPNqPg1f5zJvJVkeo30cBX1lkfvg2a7C21TYrvXFwVzbccS+7VkuzaO5peWWUwd3yt1lRA== X-Received: by 10.46.75.26 with SMTP id y26mr2324930lja.113.1509272030542; Sun, 29 Oct 2017 03:13:50 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:49 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:32 +0100 Message-Id: <20171029101343.15544-3-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v5 02/13] m25p80: Add support for SST READ ID 0x90/0xAB commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacuter ID and device ID. Signed-off-by: Francisco Iglesias Acked-by: Alistair Francis Acked-by: Marcin Krzemiński --- hw/block/m25p80.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 2971519..7a5c137 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -355,6 +355,8 @@ typedef enum { DPP = 0xa2, QPP = 0x32, QPP_4 = 0x34, + RDID_90 = 0x90, + RDID_AB = 0xab, ERASE_4K = 0x20, ERASE4_4K = 0x21, @@ -405,6 +407,7 @@ typedef enum { MAN_MACRONIX, MAN_NUMONYX, MAN_WINBOND, + MAN_SST, MAN_GENERIC, } Manufacturer; @@ -476,6 +479,8 @@ static inline Manufacturer get_man(Flash *s) return MAN_SPANSION; case 0xC2: return MAN_MACRONIX; + case 0xBF: + return MAN_SST; default: return MAN_GENERIC; } @@ -711,6 +716,22 @@ static void complete_collecting_data(Flash *s) case WEVCR: s->enh_volatile_cfg = s->data[0]; break; + case RDID_90: + case RDID_AB: + if (get_man(s) == MAN_SST && s->cur_addr <= 1) { + if (s->cur_addr) { + s->data[0] = s->pi->id[2]; + s->data[1] = s->pi->id[0]; + } else { + s->data[0] = s->pi->id[0]; + s->data[1] = s->pi->id[2]; + } + s->pos = 0; + s->len = 2; + s->data_read_loop = true; + s->state = STATE_READING_DATA; + } + break; default: break; } @@ -926,6 +947,8 @@ static void decode_new_cmd(Flash *s, uint32_t value) case PP4: case PP4_4: case DIE_ERASE: + case RDID_90: + case RDID_AB: s->needed_bytes = get_addr_length(s); s->pos = 0; s->len = 0; From patchwork Sun Oct 29 10:13:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MIfI0hP5"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtpC1cSkz9t0F for ; Sun, 29 Oct 2017 21:17:22 +1100 (AEDT) Received: from localhost ([::1]:35468 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kec-0000F0-H9 for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:17:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbK-0006UR-Hh for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbJ-0007px-K7 for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:54 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:55085) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbJ-0007pR-DB for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:53 -0400 Received: by mail-lf0-x242.google.com with SMTP id a2so11637360lfh.11 for ; Sun, 29 Oct 2017 03:13:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vrR3H5hGfnA2aTla5ccrl66sGlVMe3bSdnKTzLO2pcE=; b=MIfI0hP5SW90DiN/V0U/fwUgw4wNVi16jufMZijtvyFD2r2cggbOmIRabksMcQi9IT Qi/zk2R7ITk+G5xTnHFJJgtl1kOp5QBa2adBfqmRQUcs4IS9RVLQ3Ou64gWGn3/kf6ef 25BdaSTsQPAKdfGrvS+d7dfvM4w0zPYg0Z+UvT4bvobKC07f3m0PaU+jyfuPTcLVnmJN dr9qq6j/GdAbZKQ3EOhDJ0xhxPBsbBilUuz84akGlsNRT1i6HMhNM1b3hA56Ms3RBkbU fYAeqzJlUM0NmzOQ1YY5QTf2PyOI3EiiqQDgZA4DbSHOdQbbSwwiQzsxVf1O0SqYkuG8 i9QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vrR3H5hGfnA2aTla5ccrl66sGlVMe3bSdnKTzLO2pcE=; b=tSLaxmievBu6YUoDXhbf516NI15RmrYOQrXVMnORDMfRvfPZUycxCjnPINN8X1c1r1 X9ysp7KHImB68R/QiD04U4Okx7+TxfxVZx8IRdsuxHzh/s0nooF7Hm0ZTG8vRXymjMSt jGJTLGafI8FQv8ppvB9V7bfsfqGdJpxvdDzL0TOFTxZfdQ5F68lgpcldhGmwWSq/Douw sivFWlyJK6hIYpksoePZH12VK7sNyUW9T63DqJNYjQYBtn/VSRm0JBZPEXeb07sVr4Xw AkfdDfF4Mljwxybma5tYJcPTenfHLBtL8arzboZ4e0iZtCMDUj/hmDCiL3m9PxCmv1J/ 5O8Q== X-Gm-Message-State: AMCzsaX9D9XVJMury5cI9oXtm91gEivdeGg7kNwWni1HnXIPQFyUhwTO 8nx5dAN25GM5Kk54QArmb+KxUw== X-Google-Smtp-Source: ABhQp+Sc9lL4ucZxAaQpy0v6FOV3/l3DsEs/+bdDVZ3GtpEg0xK6CNvM2j1DZDFLhWbAUZDx2WXsbw== X-Received: by 10.46.20.15 with SMTP id u15mr2396673ljd.9.1509272031921; Sun, 29 Oct 2017 03:13:51 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:51 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:33 +0100 Message-Id: <20171029101343.15544-4-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: [Qemu-devel] [PATCH v5 03/13] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemiński --- hw/block/m25p80.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 7a5c137..cf39e36 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -331,7 +331,10 @@ typedef enum { WRDI = 0x4, RDSR = 0x5, WREN = 0x6, + BRRD = 0x16, + BRWR = 0x17, JEDEC_READ = 0x9f, + BULK_ERASE_60 = 0x60, BULK_ERASE = 0xc7, READ_FSR = 0x70, RDCR = 0x15, @@ -704,6 +707,7 @@ static void complete_collecting_data(Flash *s) s->write_enable = false; } break; + case BRWR: case EXTEND_ADDR_WRITE: s->ear = s->data[0]; break; @@ -1041,6 +1045,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) s->state = STATE_READING_DATA; break; + case BULK_ERASE_60: case BULK_ERASE: if (s->write_enable) { DB_PRINT_L(0, "chip erase\n"); @@ -1058,12 +1063,14 @@ static void decode_new_cmd(Flash *s, uint32_t value) case EX_4BYTE_ADDR: s->four_bytes_address_mode = false; break; + case BRRD: case EXTEND_ADDR_READ: s->data[0] = s->ear; s->pos = 0; s->len = 1; s->state = STATE_READING_DATA; break; + case BRWR: case EXTEND_ADDR_WRITE: if (s->write_enable) { s->needed_bytes = 1; From patchwork Sun Oct 29 10:13:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831699 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jkyauNCT"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtlG0G7dz9sxR for ; Sun, 29 Oct 2017 21:14:50 +1100 (AEDT) Received: from localhost ([::1]:35456 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kcB-0006bC-UM for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:14:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbL-0006VH-OK for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbK-0007qi-SW for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:55 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:46075) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbK-0007q7-Kq for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:54 -0400 Received: by mail-lf0-x244.google.com with SMTP id n69so11664546lfn.2 for ; Sun, 29 Oct 2017 03:13:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4i4imF3pBwlnsBAQajAxQ+7z1sSxOni8Kj3UeUJax4M=; b=jkyauNCTdJrox69cWghCcSIiIfwqy+WP/I68CzV737MS9ebkt4vn5m+2uMgce4jMAW pKNK/PXxDvFApj3UPVSWddrVx95vrwH9q//GYTElrGfnSiLOlI2xxU/wvg30y2s32iR3 NfmbjiCmM9zoLLD0zb8asasPapgQgVt6lX2kmdQqPXwHRkpYTqVJyUmfXnOegkgkBVyO Ge1BkcIGhNBTLfxrgartKXCN+XNfU6yiOueqp46y59jBf55EIDbk+sG6x5fG3k2rx0EA 5UsUYrAGIP2/r1Jo43DaL4crJGUlhUTNBjL0OWrvYhkuCIiG9jrZgPIcyA5I/VpLUs6H 5Hzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4i4imF3pBwlnsBAQajAxQ+7z1sSxOni8Kj3UeUJax4M=; b=Ww3wz5ddY2eu/QibrtWyF8SBY7cQkYGnR8VSA987n9MtW+OA35rjluSxioKo7qX/r1 ejOeoBmPBLJe3l2eRPj1ikKmqH+t8AZcb9wF0UNiAYjUwAIs6K+KQlKbPucZ46yLtaBW RuYVh/VYr7WXT+ga2+xwkDcYWMfqqaHERwnZDdSyL+fQQi8UmoFzXsaNoFVBs+VLyRZ8 KbKPWpYfhgWA7O2Nsf3mZ2i4m+mIOgvRcYnvgUEtwQpWPRWaklPLu30V8i8JGpLi2a3B QGGxNxZLtjUfLoRzLjfridzPO59srSdb4i/3KNlN/ca6nnCyWMAfNrLuXLMVPmjxLou2 5YXA== X-Gm-Message-State: AMCzsaXaJwpRx5CfWxXWGKwi6na5q298aUAg1y/2HDqNESuiw//BJHvo TNrHiCTh0G3n5NK5NcysdWJIog== X-Google-Smtp-Source: ABhQp+SCI961Cj0jzan8OZcaVejYyIi9WA/uAxnIcLka3xxBDrDXIYFZ+erFZJKn12Wv1HaXLoERHQ== X-Received: by 10.46.70.26 with SMTP id t26mr2153206lja.181.1509272033201; Sun, 29 Oct 2017 03:13:53 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:52 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:34 +0100 Message-Id: <20171029101343.15544-5-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v5 04/13] m25p80: Add support for n25q512a11 and n25q512a13 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes. Signed-off-by: Francisco Iglesias Acked-by: Marcin Krzemiński Reviewed-by: Alistair Francis --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index cf39e36..054dc6f 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -240,6 +240,8 @@ static const FlashPartInfo known_devices[] = { { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, + { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, + { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, From patchwork Sun Oct 29 10:13:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831704 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SKUMLJK5"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtpY4wSzz9t0F for ; Sun, 29 Oct 2017 21:17:41 +1100 (AEDT) Received: from localhost ([::1]:35470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kex-0000i4-Ml for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:17:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46044) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbQ-0006ZD-Pf for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbM-0007rZ-QB for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:00 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:50899) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbM-0007r0-5L for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:56 -0400 Received: by mail-lf0-x243.google.com with SMTP id a132so11641824lfa.7 for ; Sun, 29 Oct 2017 03:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=d2LdmCsfS3KEKB+Rj4ebP3cd2+seSDFhzNv0JKmY594=; b=SKUMLJK58RieQoKpBBD5ySLlxo2F/iCcOY+9aXBvBs3yMmDepqD2ETHk3We4PjCxI1 dAQZCyDtDne75ZN/PmWh/cR4vsF5J7/mIZSw2Po2HnYP5+otgmjsPo5VQXzUGooK+ng8 f9WEOTGkVVEmyyIu7aSXeM6CMvxUt64pNOcgoYYlhz732xlhNbdi9zBvcd6ziDcrFqa1 jFj2I50dWHzaJhT45tP7k3yWr961SySw0N4k/jAazlzIuEtnx/uNXkpbdtFFYBMe8Id8 HNxTU92YP1IQlD/JPeMsydsyCcqHo+jdVQeZ88mhZFms55e5HPLWuBBp82qIBJe1C06G zAjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d2LdmCsfS3KEKB+Rj4ebP3cd2+seSDFhzNv0JKmY594=; b=Aec5dPSRQfZylpllrpqing34RybZ1R6veEgEGuTyVSfQcubaMKH1HXby2CmoCpvREA 8Hxvg6j6d0rCr1xwuATK9V+3PhKxs/nYG71T/MHKSNDOVWfurRpcDTLzw4jjB7K/D2B4 opuGYmlboQHv3ky4uqXDjABdE4LRLS4xMFe4MBHQARuw3HpqTfrvPgG9vXTBIoZl7LXX pOEkrGcEOqpxSE7e3fJ1cuWTzYx6C257lg8U8/y+8AORHdOEfnDSf7uHfwtXdxsQDlvB avjvy1PgU2L3rz32izUkI/YuCHWyzbjRC/YuOEJPbc589Pc5eWUOrqjBmdWA6w5VGwcP T9kA== X-Gm-Message-State: AMCzsaVj5n8BKb8+9YHJDAdJpIS78M1Ka2r9MMWiRWq7Rhno8DyDUj2z UD43ttpZokpIhobVTDEFBv6XmA== X-Google-Smtp-Source: ABhQp+TYJg7kUAAGP83mAzMiAZ//cEYP42p5cYqvwfGO7X2mGWAFX3eW0VUc6kg3JT+Pr1Nogh4qWg== X-Received: by 10.25.23.214 with SMTP id 83mr1726504lfx.213.1509272034694; Sun, 29 Oct 2017 03:13:54 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:53 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:35 +0100 Message-Id: <20171029101343.15544-6-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v5 05/13] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency. Also move out a define and remove two dubbel included headers (while touching the code). Finally, add 4 byte address commands to the FlashCMD enum. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 35 ----------------------------------- include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 35 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ef56d35..559fa79 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -27,8 +27,6 @@ #include "sysemu/sysemu.h" #include "hw/ptimer.h" #include "qemu/log.h" -#include "qemu/fifo8.h" -#include "hw/ssi/ssi.h" #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" @@ -116,44 +114,11 @@ /* 16MB per linear region */ #define LQSPI_ADDRESS_BITS 24 -/* Bite off 4k chunks at a time */ -#define LQSPI_CACHE_SIZE 1024 #define SNOOP_CHECKING 0xFF #define SNOOP_NONE 0xFE #define SNOOP_STRIPING 0 -typedef enum { - READ = 0x3, - FAST_READ = 0xb, - DOR = 0x3b, - QOR = 0x6b, - DIOR = 0xbb, - QIOR = 0xeb, - - PP = 0x2, - DPP = 0xa2, - QPP = 0x32, -} FlashCMD; - -typedef struct { - XilinxSPIPS parent_obj; - - uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; - hwaddr lqspi_cached_addr; - Error *migration_blocker; - bool mmio_execution_enabled; -} XilinxQSPIPS; - -typedef struct XilinxSPIPSClass { - SysBusDeviceClass parent_class; - - const MemoryRegionOps *reg_ops; - - uint32_t rx_fifo_size; - uint32_t tx_fifo_size; -} XilinxSPIPSClass; - static inline int num_effective_busses(XilinxSPIPS *s) { return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa096..7f9e2fc 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; #define XLNX_SPIPS_R_MAX (0x100 / 4) +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ = 0x3, READ_4 = 0x13, + FAST_READ = 0xb, FAST_READ_4 = 0x0c, + DOR = 0x3b, DOR_4 = 0x3c, + QOR = 0x6b, QOR_4 = 0x6c, + DIOR = 0xbb, DIOR_4 = 0xbc, + QIOR = 0xeb, QIOR_4 = 0xec, + + PP = 0x2, PP_4 = 0x12, + DPP = 0xa2, + QPP = 0x32, QPP_4 = 0x34, +} FlashCMD; + struct XilinxSPIPS { SysBusDevice parent_obj; @@ -56,6 +72,24 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; }; +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" From patchwork Sun Oct 29 10:13:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831706 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; 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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:55 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:36 +0100 Message-Id: <20171029101343.15544-7-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v5 06/13] xilinx_spips: Update striping to be big-endian bit order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Update striping functionality to be big-endian bit order and output even bits into flash memory connected to the lower QSPI bus and odd bits into the flash memory connected to the upper QSPI bus. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 559fa79..7accf5d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -208,14 +208,14 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } -/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) +/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num == 3): * - * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } - * { hgfedcba, } { GDAfc741, } - * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} + * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } + * { hgfedcba, } { 630fcHEB, } + * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} */ static inline void stripe8(uint8_t *x, int num, bool dir) @@ -223,15 +223,15 @@ static inline void stripe8(uint8_t *x, int num, bool dir) uint8_t r[num]; memset(r, 0, sizeof(uint8_t) * num); int idx[2] = {0, 0}; - int bit[2] = {0, 0}; + int bit[2] = {0, 7}; int d = dir; for (idx[0] = 0; idx[0] < num; ++idx[0]) { - for (bit[0] = 0; bit[0] < 8; ++bit[0]) { - r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; + for (bit[0] = 7; bit[0] != -1; bit[0] += -1) { + r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; idx[1] = (idx[1] + 1) % num; if (!idx[1]) { - bit[1]++; + bit[1] += -1; } } } @@ -266,8 +266,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } for (i = 0; i < num_effective_busses(s); ++i) { + int bus = num_effective_busses(s) - 1 - i; DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); - tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); + tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); } From patchwork Sun Oct 29 10:13:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831707 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Kmu0lbpQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtsm0pXbz9t0F for ; Sun, 29 Oct 2017 21:20:28 +1100 (AEDT) Received: from localhost ([::1]:35477 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8khe-0002mA-1t for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:20:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbS-0006aQ-8i for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbP-0007sa-EK for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:02 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:48803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbP-0007sC-2I for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:13:59 -0400 Received: by mail-lf0-x244.google.com with SMTP id a69so11661275lfe.5 for ; Sun, 29 Oct 2017 03:13:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LLPSYFC4X6giAbTrrYQFJJs+vZkinyiqhd7d2s3gTmE=; b=Kmu0lbpQviabs6ifNkaTJbL/KxNisiNwNcmRAdJKaIRx2Am+77E9Y1HosmsgKjUokv 4HV5ZX31CeTs+sro8VGgNQDtQpJf2qafr6Mw+MbDYMaumHpA5utxrdUAJ5dA6ciBccoI xqawrW5B2mH8JPETXH2NQRXhXtCwOfQpaW9FeyOp30xh8Uq2OTx+NzkoVVkhM9zV5oQG 3ZibthRm7/rnwm25Boe/Z09vf6RlN6GR/EwO+Y97sXtt8mcLWvAR68QPg6DZ7pEP8tbI B5aVpemZih5QXD/VyFnTryOlmkbzHUGVofxjXsbowwcqfufTAT/O2og7dweu8QHcY8/i 6lWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LLPSYFC4X6giAbTrrYQFJJs+vZkinyiqhd7d2s3gTmE=; b=qJWWRq9cvhdEpc9l3S7nNZ6Tj3E7EDZhvUyXsbuLuP0rtNKygEkfiXUd8TEfj4WGpD KrsM6xA0/JCzN/71vvHWICggPjnv5mGMjg2j+OVuqyCDbXYi8T+yOCBirsk1MUsfNvpn E2VINIZ5lzvjo7Nf3GdBmD+bM1BOvfddDKRRQDcEWhmJ4xlBHc2VSBW6jBaN0utnZ4Ce ESkIQ7PJM6KcDyKhXsFLZrLhPpB8xgeUf5arKAoiy/1ZEw1lr4fe65t3dlLvN6U8Sh/b AQdtgCYPb/oB527vlYPMVRKug9wdMwb5igDAkCaWz1cDwveGBWd1sKu2t2iWJWMS9ceS rLDA== X-Gm-Message-State: AMCzsaWZmsuLFOCiHtByKMrwRjSE7wccKQpoOpM6Vdk8j+FUOg/ZXmkq c6MCiGbcOoV97vVGAfKn09sc7A== X-Google-Smtp-Source: ABhQp+S1TnRV/FY+tFzbEqRFDqtSU811SwkWxNY4rAkAV6nHSeIMh6D5mIFs7+MPWGbwfMkcrtyeog== X-Received: by 10.25.211.84 with SMTP id k81mr1798692lfg.120.1509272037506; Sun, 29 Oct 2017 03:13:57 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:56 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:37 +0100 Message-Id: <20171029101343.15544-8-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v5 07/13] xilinx_spips: Add support for RX discard and RX drain X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the RX discard and RX drain functionality. Also transmit one byte per dummy cycle (to the flash memories) with commands that require these. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 167 +++++++++++++++++++++++++++++++++++++----- include/hw/ssi/xilinx_spips.h | 6 ++ 2 files changed, 155 insertions(+), 18 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7accf5d..8634810 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -30,6 +30,7 @@ #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" +#include "hw/register.h" #include "migration/blocker.h" #ifndef XILINX_SPIPS_ERR_DEBUG @@ -100,6 +101,14 @@ #define LQSPI_CFG_DUMMY_SHIFT 8 #define LQSPI_CFG_INST_CODE 0xFF +#define R_CMND (0xc0 / 4) + #define R_CMND_RXFIFO_DRAIN (1 << 19) + FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) +#define R_CMND_EXT_ADD (1 << 15) + FIELD(CMND, RX_DISCARD, 8, 7) + FIELD(CMND, DUMMY_CYCLES, 2, 6) +#define R_CMND_DMA_EN (1 << 1) +#define R_CMND_PUSH_WAIT (1 << 0) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) @@ -116,7 +125,8 @@ #define LQSPI_ADDRESS_BITS 24 #define SNOOP_CHECKING 0xFF -#define SNOOP_NONE 0xFE +#define SNOOP_ADDR 0xF0 +#define SNOOP_NONE 0xEE #define SNOOP_STRIPING 0 static inline int num_effective_busses(XilinxSPIPS *s) @@ -146,9 +156,14 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) if (xilinx_spips_cs_is_set(s, i, field) && !found) { DB_PRINT_L(0, "selecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 0); + if (s->cs_lines_state[cs_to_set]) { + s->cs_lines_state[cs_to_set] = false; + s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + } } else { DB_PRINT_L(0, "deselecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 1); + s->cs_lines_state[cs_to_set] = true; } } if (xilinx_spips_cs_is_set(s, i, field)) { @@ -157,6 +172,10 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) } if (!found) { s->snoop_state = SNOOP_CHECKING; + s->cmd_dummies = 0; + s->link_state = 1; + s->link_state_next = 1; + s->link_state_next_when = 0; DB_PRINT_L(1, "moving to snoop check state\n"); } } @@ -203,7 +222,11 @@ static void xilinx_spips_reset(DeviceState *d) /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] = 0x01090106; s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; + s->link_state = 1; + s->link_state_next = 1; + s->link_state_next_when = 0; s->snoop_state = SNOOP_CHECKING; + s->cmd_dummies = 0; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -238,14 +261,69 @@ static inline void stripe8(uint8_t *x, int num, bool dir) memcpy(x, r, sizeof(uint8_t) * num); } +static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) +{ + if (!qs) { + /* The SPI device is not a QSPI device */ + return -1; + } + + switch (command) { /* check for dummies */ + case READ: /* no dummy bytes/cycles */ + case PP: + case DPP: + case QPP: + case READ_4: + case PP_4: + case QPP_4: + return 0; + case FAST_READ: + case DOR: + case QOR: + case DOR_4: + case QOR_4: + return 1; + case DIOR: + case FAST_READ_4: + case DIOR_4: + return 2; + case QIOR: + case QIOR_4: + return 5; + default: + return -1; + } +} + +static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) +{ + switch (cmd) { + case PP_4: + case QPP_4: + case READ_4: + case QIOR_4: + case FAST_READ_4: + case DOR_4: + case QOR_4: + case DIOR_4: + return 4; + default: + return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; + } +} + static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) { int debug_level = 0; + XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), + TYPE_XILINX_QSPIPS); for (;;) { int i; uint8_t tx = 0; uint8_t tx_rx[num_effective_busses(s)]; + uint8_t dummy_cycles = 0; + uint8_t addr_length; if (fifo8_is_empty(&s->tx_fifo)) { if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { @@ -258,54 +336,102 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] = fifo8_pop(&s->tx_fifo); } stripe8(tx_rx, num_effective_busses(s), false); - } else { + } else if (s->snoop_state >= SNOOP_ADDR) { tx = fifo8_pop(&s->tx_fifo); for (i = 0; i < num_effective_busses(s); ++i) { tx_rx[i] = tx; } + } else { + /* Extract a dummy byte and generate dummy cycles according to the + * link state */ + tx = fifo8_pop(&s->tx_fifo); + dummy_cycles = 8 / s->link_state; } for (i = 0; i < num_effective_busses(s); ++i) { int bus = num_effective_busses(s) - 1 - i; - DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); - tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); - DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); + if (dummy_cycles) { + int d; + for (d = 0; d < dummy_cycles; ++d) { + tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); + } + } else { + DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); + tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); + DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); + } } - if (fifo8_is_full(&s->rx_fifo)) { + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); + /* Do nothing */ + } else if (s->rx_discard) { + DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); + s->rx_discard -= 8 / s->link_state; + } else if (fifo8_is_full(&s->rx_fifo)) { s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; DB_PRINT_L(0, "rx FIFO overflow"); } else if (s->snoop_state == SNOOP_STRIPING) { stripe8(tx_rx, num_effective_busses(s), true); for (i = 0; i < num_effective_busses(s); ++i) { fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); + DB_PRINT_L(debug_level, "pushing striped rx byte\n"); } } else { + DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); } + if (s->link_state_next_when) { + s->link_state_next_when--; + if (!s->link_state_next_when) { + s->link_state = s->link_state_next; + } + } + DB_PRINT_L(debug_level, "initial snoop state: %x\n", (unsigned)s->snoop_state); switch (s->snoop_state) { case (SNOOP_CHECKING): - switch (tx) { /* new instruction code */ - case READ: /* 3 address bytes, no dummy bytes/cycles */ - case PP: + /* Store the count of dummy bytes in the txfifo */ + s->cmd_dummies = xilinx_spips_num_dummies(q, tx); + addr_length = get_addr_length(s, tx); + if (s->cmd_dummies < 0) { + s->snoop_state = SNOOP_NONE; + } else { + s->snoop_state = SNOOP_ADDR + addr_length - 1; + } + switch (tx) { case DPP: - case QPP: - s->snoop_state = 3; - break; - case FAST_READ: /* 3 address bytes, 1 dummy byte */ case DOR: + case DOR_4: + s->link_state_next = 2; + s->link_state_next_when = addr_length + s->cmd_dummies; + break; + case QPP: + case QPP_4: case QOR: - case DIOR: /* FIXME: these vary between vendor - set to spansion */ - s->snoop_state = 4; + case QOR_4: + s->link_state_next = 4; + s->link_state_next_when = addr_length + s->cmd_dummies; + break; + case DIOR: + case DIOR_4: + s->link_state = 2; break; - case QIOR: /* 3 address bytes, 2 dummy bytes */ - s->snoop_state = 6; + case QIOR: + case QIOR_4: + s->link_state = 4; break; - default: + } + break; + case (SNOOP_ADDR): + /* Address has been transmitted, transmit dummy cycles now if + * needed */ + if (s->cmd_dummies < 0) { s->snoop_state = SNOOP_NONE; + } else { + s->snoop_state = s->cmd_dummies; } break; case (SNOOP_STRIPING): @@ -483,6 +609,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { XilinxQSPIPS *q = XILINX_QSPIPS(opaque); + XilinxSPIPS *s = XILINX_SPIPS(opaque); xilinx_spips_write(opaque, addr, value, size); addr >>= 2; @@ -490,6 +617,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, if (addr == R_LQSPI_CFG) { xilinx_qspips_invalidate_mmio_ptr(q); } + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + fifo8_reset(&s->rx_fifo); + } } static const MemoryRegionOps qspips_ops = { @@ -632,6 +762,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) } s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); + s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 7f9e2fc..bac90a5 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -61,13 +61,19 @@ struct XilinxSPIPS { uint8_t num_busses; uint8_t snoop_state; + int cmd_dummies; + uint8_t link_state; + uint8_t link_state_next; + uint8_t link_state_next_when; qemu_irq *cs_lines; + bool *cs_lines_state; SSIBus **spi; Fifo8 rx_fifo; Fifo8 tx_fifo; uint8_t num_txrx_bytes; + uint32_t rx_discard; uint32_t regs[XLNX_SPIPS_R_MAX]; }; From patchwork Sun Oct 29 10:13:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v5 08/13] xilinx_spips: Make tx/rx_data_bytes more generic and reusable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Make tx/rx_data_bytes more generic so they can be reused (when adding support for the Zynqmp Generic QSPI). Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 64 +++++++++++++++++++++++++++++---------------------- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8634810..e37d005 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -47,7 +47,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) #define IFMODE (1U << 31) -#define ENDIAN (1 << 26) +#define R_CONFIG_ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) #define MAN_START_EN (1 << 15) @@ -450,13 +450,28 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } } -static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) +static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) { int i; + for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { + if (be) { + fifo8_push(fifo, (uint8_t)(value >> 24)); + value <<= 8; + } else { + fifo8_push(fifo, (uint8_t)value); + value >>= 8; + } + } +} - for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { - value[i] = fifo8_pop(&s->rx_fifo); +static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) +{ + int i; + + for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { + value[i] = fifo8_pop(fifo); } + return max - i; } static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, @@ -466,6 +481,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, uint32_t mask = ~0; uint32_t ret; uint8_t rx_buf[4]; + int shortfall; addr >>= 2; switch (addr) { @@ -496,9 +512,13 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, break; case R_RX_DATA: memset(rx_buf, 0, sizeof(rx_buf)); - rx_data_bytes(s, rx_buf, s->num_txrx_bytes); - ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) - : cpu_to_le32(*(uint32_t *)rx_buf); + shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); + ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { + ret <<= 8 * shortfall; + } DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; @@ -509,20 +529,6 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, } -static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) -{ - int i; - for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { - if (s->regs[R_CONFIG] & ENDIAN) { - fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); - value <<= 8; - } else { - fifo8_push(&s->tx_fifo, (uint8_t)value); - value >>= 8; - } - } -} - static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -563,16 +569,20 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, mask = 0; break; case R_TX_DATA: - tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD1: - tx_data_bytes(s, (uint32_t)value, 1); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD2: - tx_data_bytes(s, (uint32_t)value, 2); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD3: - tx_data_bytes(s, (uint32_t)value, 3); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); @@ -682,11 +692,11 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) while (cache_entry < LQSPI_CACHE_SIZE) { for (i = 0; i < 64; ++i) { - tx_data_bytes(s, 0, 1); + tx_data_bytes(&s->tx_fifo, 0, 1, false); } xilinx_spips_flush_txfifo(s); for (i = 0; i < 64; ++i) { - rx_data_bytes(s, &q->lqspi_buf[cache_entry++], 1); + rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); } } From patchwork Sun Oct 29 10:13:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831700 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.13.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:13:59 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:39 +0100 Message-Id: <20171029101343.15544-10-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 Subject: [Qemu-devel] [PATCH v5 09/13] xilinx_spips: Add support for zero pumping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for zero pumping according to the transfer size register. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 47 ++++++++++++++++++++++++++++++++++++------- include/hw/ssi/xilinx_spips.h | 2 ++ 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e37d005..3a98799 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ FIELD(CMND, DUMMY_CYCLES, 2, 6) #define R_CMND_DMA_EN (1 << 1) #define R_CMND_PUSH_WAIT (1 << 0) +#define R_TRANSFER_SIZE (0xc4 / 4) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) @@ -227,6 +228,7 @@ static void xilinx_spips_reset(DeviceState *d) s->link_state_next_when = 0; s->snoop_state = SNOOP_CHECKING; s->cmd_dummies = 0; + s->man_start_com = false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -464,6 +466,41 @@ static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) } } +static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) +{ + if (!s->regs[R_TRANSFER_SIZE]) { + return; + } + if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { + return; + } + /* + * The zero pump must never fill tx fifo such that rx overflow is + * possible + */ + while (s->regs[R_TRANSFER_SIZE] && + s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { + /* endianess just doesn't matter when zero pumping */ + tx_data_bytes(&s->tx_fifo, 0, 4, false); + s->regs[R_TRANSFER_SIZE] &= ~0x03ull; + s->regs[R_TRANSFER_SIZE] -= 4; + } +} + +static void xilinx_spips_check_flush(XilinxSPIPS *s) +{ + if (s->man_start_com || + (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } + if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { + s->man_start_com = false; + } + xilinx_spips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -533,7 +570,6 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { int mask = ~0; - int man_start_com = 0; XilinxSPIPS *s = opaque; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); @@ -541,8 +577,8 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, switch (addr) { case R_CONFIG: mask = ~(R_CONFIG_RSVD | MAN_START_COM); - if (value & MAN_START_COM) { - man_start_com = 1; + if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { + s->man_start_com = true; } break; case R_INTR_STATUS: @@ -588,10 +624,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: xilinx_spips_update_cs_lines(s); - if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || - (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { - xilinx_spips_flush_txfifo(s); - } + xilinx_spips_check_flush(s); xilinx_spips_update_cs_lines(s); xilinx_spips_update_ixr(s); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index bac90a5..ad2175a 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -76,6 +76,8 @@ struct XilinxSPIPS { uint32_t rx_discard; uint32_t regs[XLNX_SPIPS_R_MAX]; + + bool man_start_com; }; typedef struct { From patchwork Sun Oct 29 10:13:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831710 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ELBCU9tv"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtww5bbdz9t1t for ; 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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.14.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:14:00 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:40 +0100 Message-Id: <20171029101343.15544-11-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v5 10/13] xilinx_spips: Add support for 4 byte addresses in the LQSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 3a98799..7f0f317 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -92,8 +92,9 @@ #define R_LQSPI_CFG_RESET 0x03A002EB #define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) -#define LQSPI_CFG_SEP_BUS (1 << 30) +#define LQSPI_CFG_SEP_BUS (1 << 29) #define LQSPI_CFG_U_PAGE (1 << 28) +#define LQSPI_CFG_ADDR4 (1 << 27) #define LQSPI_CFG_MODE_EN (1 << 25) #define LQSPI_CFG_MODE_WIDTH 8 #define LQSPI_CFG_MODE_SHIFT 16 @@ -702,6 +703,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); /* read address */ DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { + fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); + } fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); From patchwork Sun Oct 29 10:13:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831709 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nKDcKtfx"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtwv0MKMz9t1t for ; Sun, 29 Oct 2017 21:23:07 +1100 (AEDT) Received: from localhost ([::1]:35493 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kkB-00055F-6j for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:23:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46103) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbV-0006dW-E1 for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbU-0007ut-Fw for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:05 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:49333) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbU-0007uQ-8x for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:04 -0400 Received: by mail-lf0-x241.google.com with SMTP id w21so11682134lfc.6 for ; Sun, 29 Oct 2017 03:14:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Kd3Ts2sK0qM5EZrgstgg3un17UPdc18uEXx8/KI/71Y=; b=nKDcKtfxvBmPAVmbJ1AXKpmrp1AG9yyH3WgP1XJUHoRys36YbZDrbmvo+MYYGhr+0b qRsrFqyRDhFuOGkniaHIYUlo+uo1aS2OKP2bDBdG5zjY9YM0OnLe5hgbW2gvkXzpu44V k/hwXrIYCPs5BBHwhVGDbIQvJJ3UVj9/N5BZlFONrC5kTWkmd/OXDCI2QTdGeFvXvRT1 vB0Olo/WMbXkevL+MKNJuNt8P+orqQrvtTrJgnhSViGfQWHb0ZoFPU/78r32mLrxi+Nj iEumXw18L+MPI26WZVdvwdNucK+MqYReRbgWSiMWQ0TyKIJmX0doqqF336vz4cgRMrpw aJlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Kd3Ts2sK0qM5EZrgstgg3un17UPdc18uEXx8/KI/71Y=; b=S1wWbR7+/99c4e8Kwl76+uQzMvbN+JZmjlfanyiyMnNzGa2cWJ3p5reGN90NYhKWTj bhnDK4c9MoXDx5owWrZGAYZo4L6qT1eHMLUrO4CK7z5JkBStv2PaEbj+0YJd/k5rRmnF 7KGTYH7I6vOEEty6dg/CifKdBkJME6ReIwL11vgYL2oajgSgJl5DYeHqj3pWgDbhhpwk m5jGgNAtNrNfBGISgRnT5lZ2T8Q/nXf19pln7qMg1Y4swf2E6V4B5DE2S3tnMeA8e7y6 F9/2B8PXK6arVwa7iaHJUOrTFhdTxao3KdmWOT+CwTKIRY30gXOQ7F1remOgAoeV53NP mWGg== X-Gm-Message-State: AMCzsaVmE/gXaoox2tU9jTmyeLGZNnTK3J0d5lfqWOJTSFFXMfY1Mula fTCjsMt5tnqIp8eiir+5vj8VYw== X-Google-Smtp-Source: ABhQp+TCrpHByYmAqvrRSE+dslfezs2rmmLt+P2fn1+YeJ3EB77QqrqXVyQn4EM8h+vEJ+0IQ+DBXQ== X-Received: by 10.25.151.206 with SMTP id z197mr1707032lfd.3.1509272042822; Sun, 29 Oct 2017 03:14:02 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.14.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:14:02 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:41 +0100 Message-Id: <20171029101343.15544-12-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v5 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7f0f317..159a89d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state == SNOOP_STRIPING) { @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask = IXR_ALL; From patchwork Sun Oct 29 10:13:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831711 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vb6nVWx/"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtzP26D3z9t1t for ; Sun, 29 Oct 2017 21:25:21 +1100 (AEDT) Received: from localhost ([::1]:35502 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kmN-0006jG-Ap for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:25:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbZ-0006hJ-7p for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbW-0007vZ-EP for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:09 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:44386) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbV-0007vB-U5 for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:06 -0400 Received: by mail-lf0-x241.google.com with SMTP id 75so11679057lfx.1 for ; Sun, 29 Oct 2017 03:14:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wnOLbplJYGoznIstspvMi1pfZ0/79nQMaFbsYnXmvrg=; b=vb6nVWx/SvcqLIfUUXun6fYBVqyeo04sZF4Pghek9cbfkbO01mgFbUBdmS0Qh4MqcC tv1wa5HD8WADXuvF3VJN0uiv536Z/d6t1iYxbb17wQVY+epv+KH5vxVwrfPXgArNSP2j ELQdansj25HjeoN10iOV1VSDbYfwhouT+UVb9ZEyQt0owArqEz/aRrdCSVea79yLoXsf vY7IbV3FbafRGbeLp1C7GqfxPhqbzul+fPGpDfC2zAo0VI/uoMU2MDam6OKSmpoZ9rKb cGQvjOORZA2CgY4x50kqWcZLDS4h7pgnU+VncRUgFuoS7DdvoY+XhZ/q2kSKB9duIDwB ynAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wnOLbplJYGoznIstspvMi1pfZ0/79nQMaFbsYnXmvrg=; b=Vdt5SYQpJIaq0Rikta54cinkKuZn828r/UGwBxcbfkKz/UEql72aAJgAGwhsYYVbkJ 6Bs7cXMTHl1pYVFsInR7EfsIYOp5AXU+NkrZIN24mNeYrMFFceCmOPnDuEzMrrvHR2hn dcRSKDWBQ1zzgRnpMuS+bzbsNaeN2sRnKgAf88Tn1XD1u9lRZn9cGiKV0Wz8eK4ekH2/ imxn14ldu0VJsD/dTwS6O9EuuWrh7jvxq2/mphmX1SX1WzQGKSX+N04xL7mzM8xjN2LD tHePic6w92YHCXXe8kAvNJ4UDPET6B1Kt4wKO4Luuu8IZbk1vmOSAJczsAMXdyGHPk22 gkbw== X-Gm-Message-State: AMCzsaWMyval/WYJoruYZJanZy+ZcPkg39ZXOT+y7hwF4djR4jOddgTw tSRKopbmZ7pad40XBGYJ2VCN2g== X-Google-Smtp-Source: ABhQp+Q+o69L+Uz+CgaNXLDwrhYX9Z6Jpeb4XTiJq7KaN5MgrUBsiPIRv7G+pQaOkYEasaI5nCzvww== X-Received: by 10.25.115.14 with SMTP id o14mr1466001lfc.79.1509272044110; Sun, 29 Oct 2017 03:14:04 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.14.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:14:03 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:42 +0100 Message-Id: <20171029101343.15544-13-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v5 12/13] xilinx_spips: Add support for the ZynqMP Generic QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias --- default-configs/arm-softmmu.mak | 1 + hw/ssi/xilinx_spips.c | 449 +++++++++++++++++++++++++++++++++++----- include/hw/ssi/xilinx_spips.h | 29 ++- 3 files changed, 429 insertions(+), 50 deletions(-) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 5059d13..d09fd34 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -130,3 +130,4 @@ CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y CONFIG_MSF2=y +CONFIG_XILINX_AXI=y diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 159a89d..f8d2018 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -31,6 +31,7 @@ #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" #include "hw/register.h" +#include "sysemu/dma.h" #include "migration/blocker.h" #ifndef XILINX_SPIPS_ERR_DEBUG @@ -69,13 +70,30 @@ #define R_INTR_DIS (0x0C / 4) #define R_INTR_MASK (0x10 / 4) #define IXR_TX_FIFO_UNDERFLOW (1 << 6) +/* Poll timeout not implemented */ +#define IXR_RX_FIFO_EMPTY (1 << 11) +#define IXR_GENERIC_FIFO_FULL (1 << 10) +#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) +#define IXR_TX_FIFO_EMPTY (1 << 8) +#define IXR_GENERIC_FIFO_EMPTY (1 << 7) #define IXR_RX_FIFO_FULL (1 << 5) #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) #define IXR_TX_FIFO_FULL (1 << 3) #define IXR_TX_FIFO_NOT_FULL (1 << 2) #define IXR_TX_FIFO_MODE_FAIL (1 << 1) #define IXR_RX_FIFO_OVERFLOW (1 << 0) -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) +#define IXR_ALL ((1 << 13) - 1) +#define GQSPI_IXR_MASK 0xFBE +#define IXR_SELF_CLEAR \ +(IXR_GENERIC_FIFO_EMPTY \ +| IXR_GENERIC_FIFO_FULL \ +| IXR_GENERIC_FIFO_NOT_FULL \ +| IXR_TX_FIFO_EMPTY \ +| IXR_TX_FIFO_FULL \ +| IXR_TX_FIFO_NOT_FULL \ +| IXR_RX_FIFO_EMPTY \ +| IXR_RX_FIFO_FULL \ +| IXR_RX_FIFO_NOT_EMPTY) #define R_EN (0x14 / 4) #define R_DELAY (0x18 / 4) @@ -116,9 +134,54 @@ #define R_MOD_ID (0xFC / 4) +#define R_GQSPI_SELECT (0x144 / 4) + FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) +#define R_GQSPI_ISR (0x104 / 4) +#define R_GQSPI_IER (0x108 / 4) +#define R_GQSPI_IDR (0x10c / 4) +#define R_GQSPI_IMR (0x110 / 4) +#define R_GQSPI_TX_THRESH (0x128 / 4) +#define R_GQSPI_RX_THRESH (0x12c / 4) +#define R_GQSPI_CNFG (0x100 / 4) + FIELD(GQSPI_CNFG, MODE_EN, 30, 2) + FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) + FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) + FIELD(GQSPI_CNFG, ENDIAN, 26, 1) + /* Poll timeout not implemented */ + FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) + /* QEMU doesnt care about any of these last three */ + FIELD(GQSPI_CNFG, BR, 3, 3) + FIELD(GQSPI_CNFG, CPH, 2, 1) + FIELD(GQSPI_CNFG, CPL, 1, 1) +#define R_GQSPI_GEN_FIFO (0x140 / 4) +#define R_GQSPI_TXD (0x11c / 4) +#define R_GQSPI_RXD (0x120 / 4) +#define R_GQSPI_FIFO_CTRL (0x14c / 4) + FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) + FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) + FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) +#define R_GQSPI_GFIFO_THRESH (0x150 / 4) +#define R_GQSPI_DATA_STS (0x15c / 4) +/* We use the snapshot register to hold the core state for the currently + * or most recently executed command. So the generic fifo format is defined + * for the snapshot register + */ +#define R_GQSPI_GF_SNAPSHOT (0x160 / 4) + FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) + FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) + FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) + FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) + FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) + FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) + FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) + FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) +#define R_GQSPI_MOD_ID (0x168 / 4) +#define R_GQSPI_MOD_ID_VALUE 0x010A0000 /* size of TXRX FIFOs */ -#define RXFF_A 32 -#define TXFF_A 32 +#define RXFF_A (128) +#define TXFF_A (128) #define RXFF_A_Q (64 * 4) #define TXFF_A_Q (64 * 4) @@ -137,42 +200,54 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } -static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) +static void xilinx_spips_update_cs_lines_legacy(XilinxSPIPS *s, int *field) { - return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS - || !fifo8_is_empty(&s->tx_fifo)); + *field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); + /* In dual parallel, mirror low CS to both */ + if (num_effective_busses(s) == 2) { + /* Single bit chip-select for qspi */ + *field &= 0x1; + *field |= *field << 1; + /* Dual stack U-Page */ + } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && + s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { + /* Single bit chip-select for qspi */ + *field &= 0x1; + /* change from CS0 to CS1 */ + *field <<= 1; + } + /* Auto CS */ + if (!(s->regs[R_CONFIG] & MANUAL_CS) && + fifo8_is_empty(&s->tx_fifo)) { + *field = 0; + } } static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) { - int i, j; - bool found = false; - int field = s->regs[R_CONFIG] >> CS_SHIFT; + int i; + int field = 0; + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + xilinx_spips_update_cs_lines_legacy(s, &field); + } else if (s->regs[R_GQSPI_GF_SNAPSHOT]) { + field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); + } else { + /* Do nothing */ + return; + } for (i = 0; i < s->num_cs; i++) { - for (j = 0; j < num_effective_busses(s); j++) { - int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); - int cs_to_set = (j * s->num_cs + i + upage) % - (s->num_cs * s->num_busses); - - if (xilinx_spips_cs_is_set(s, i, field) && !found) { - DB_PRINT_L(0, "selecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 0); - if (s->cs_lines_state[cs_to_set]) { - s->cs_lines_state[cs_to_set] = false; - s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); - } - } else { - DB_PRINT_L(0, "deselecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 1); - s->cs_lines_state[cs_to_set] = true; - } - } - if (xilinx_spips_cs_is_set(s, i, field)) { - found = true; + bool old_state = s->cs_lines_state[i]; + bool new_state = field & (1 << i); + + if (old_state != new_state) { + s->cs_lines_state[i] = new_state; + s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + DB_PRINT_L(0, "%sselecting slave %d\n", new_state ? "" : "de", i); } + qemu_set_irq(s->cs_lines[i], !new_state); } - if (!found) { + if (!(field & ((1 << s->num_cs) - 1))) { s->snoop_state = SNOOP_CHECKING; s->cmd_dummies = 0; s->link_state = 1; @@ -184,22 +259,46 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) static void xilinx_spips_update_ixr(XilinxSPIPS *s) { - if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { - return; + int new_irqline; + uint32_t qspi_int; + uint32_t gqspi_int; + + s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; + s->regs[R_GQSPI_ISR] |= + (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | + (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | + (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? + IXR_GENERIC_FIFO_NOT_FULL : 0) | + (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? + IXR_TX_FIFO_NOT_FULL : 0); + + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; + s->regs[R_INTR_STATUS] |= + (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo.num >= s->regs[R_RX_THRES] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); + if (object_dynamic_cast(OBJECT(s), TYPE_XLNX_ZYNQMP_QSPIPS)) { + s->regs[R_INTR_STATUS] |= fifo8_is_empty(&s->tx_fifo) ? + IXR_TX_FIFO_EMPTY : 0; + } } - /* These are set/cleared as they occur */ - s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | - IXR_TX_FIFO_MODE_FAIL); - /* these are pure functions of fifo state, set them here */ - s->regs[R_INTR_STATUS] |= - (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | - (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | - (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | - (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); + /* QSPI/SPI Interrupt Trigger Status */ + qspi_int = s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS]; + /* GQSPI Interrupt Trigger Status */ + gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; /* drive external interrupt pin */ - int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & - IXR_ALL); + new_irqline = !!((qspi_int | gqspi_int) & IXR_ALL); if (new_irqline != s->irqline) { + DB_PRINT_L(0, "IRQ state: %x -> %x\n", s->irqline, new_irqline); s->irqline = new_irqline; qemu_set_irq(s->irq, s->irqline); } @@ -216,11 +315,18 @@ static void xilinx_spips_reset(DeviceState *d) fifo8_reset(&s->rx_fifo); fifo8_reset(&s->rx_fifo); + fifo8_reset(&s->rx_fifo_g); + fifo8_reset(&s->rx_fifo_g); + fifo32_reset(&s->fifo_g); /* non zero resets */ s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; s->regs[R_TX_THRES] = 1; s->regs[R_RX_THRES] = 1; + s->regs[R_GQSPI_TX_THRESH] = 1; + s->regs[R_GQSPI_RX_THRESH] = 1; + s->regs[R_GQSPI_GFIFO_THRESH] = 1; + s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK; /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] = 0x01090106; s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; @@ -230,6 +336,7 @@ static void xilinx_spips_reset(DeviceState *d) s->snoop_state = SNOOP_CHECKING; s->cmd_dummies = 0; s->man_start_com = false; + s->man_start_com_g = false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -264,6 +371,108 @@ static inline void stripe8(uint8_t *x, int num, bool dir) memcpy(x, r, sizeof(uint8_t) * num); } +static void xilinx_spips_flush_fifo_g(XilinxSPIPS *s) +{ + while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { + uint8_t tx_rx[2] = { 0 }; + int num_stripes = 1; + uint8_t busses; + int i; + + if (!s->regs[R_GQSPI_DATA_STS]) { + uint8_t imm; + + s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); + DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); + if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { + DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); + continue; + } + xilinx_spips_update_cs_lines(s); + + imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + /* immedate transfer */ + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + s->regs[R_GQSPI_DATA_STS] = 1; + /* CS setup/hold - do nothing */ + } else { + s->regs[R_GQSPI_DATA_STS] = 0; + } + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { + if (imm > 31) { + qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" + " long - 2 ^ %" PRId8 " requested\n", imm); + } + s->regs[R_GQSPI_DATA_STS] = 1ul << imm; + } else { + s->regs[R_GQSPI_DATA_STS] = imm; + } + } + /* Zero length transfer check */ + if (!s->regs[R_GQSPI_DATA_STS]) { + continue; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && + fifo8_is_full(&s->rx_fifo_g)) { + /* No space in RX fifo for transfer - try again later */ + return; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && + (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { + num_stripes = 2; + } + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + tx_rx[0] = ARRAY_FIELD_EX32(s->regs, + GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { + for (i = 0; i < num_stripes; ++i) { + if (!fifo8_is_empty(&s->tx_fifo_g)) { + tx_rx[i] = fifo8_pop(&s->tx_fifo_g); + s->tx_fifo_g_align++; + } else { + return; + } + } + } + if (num_stripes == 1) { + /* mirror */ + tx_rx[1] = tx_rx[0]; + } + busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); + for (i = 0; i < 2; ++i) { + DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); + tx_rx[i] = ssi_transfer(s->spi[i], tx_rx[i]); + DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); + } + if (s->regs[R_GQSPI_DATA_STS] > 1 && + busses == 0x3 && num_stripes == 2) { + s->regs[R_GQSPI_DATA_STS] -= 2; + } else if (s->regs[R_GQSPI_DATA_STS] > 0) { + s->regs[R_GQSPI_DATA_STS]--; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + for (i = 0; i < 2; ++i) { + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); + fifo8_push(&s->rx_fifo_g, tx_rx[i]); + s->rx_fifo_g_align++; + } + } + } + if (!s->regs[R_GQSPI_DATA_STS]) { + for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { + fifo8_pop(&s->tx_fifo_g); + } + for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { + fifo8_push(&s->rx_fifo_g, 0); + } + } + } +} + static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) { if (!qs) { @@ -487,15 +696,27 @@ static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) static void xilinx_spips_check_flush(XilinxSPIPS *s) { - if (s->man_start_com || - (!fifo8_is_empty(&s->tx_fifo) && - !(s->regs[R_CONFIG] & MAN_START_EN))) { - xilinx_spips_check_zero_pump(s); - xilinx_spips_flush_txfifo(s); + bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || + !fifo32_is_empty(&s->fifo_g); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (s->man_start_com_g || (gqspi_has_work && + !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { + xilinx_spips_flush_fifo_g(s); + } + } else { + if (s->man_start_com || (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } } if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { s->man_start_com = false; } + if (!gqspi_has_work) { + s->man_start_com_g = false; + } xilinx_spips_update_ixr(s); } @@ -509,6 +730,53 @@ static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) return max - i; } +static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) +{ + void *ret; + + if (max == 0 || max > fifo->num) { + abort(); + } + *num = MIN(fifo->capacity - fifo->head, max); + ret = &fifo->data[fifo->head]; + fifo->head += *num; + fifo->head %= fifo->capacity; + fifo->num -= *num; + return ret; +} + +static void xlnx_zynqmp_qspips_notify(void *opaque) +{ + XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); + XilinxSPIPS *s = XILINX_SPIPS(rq); + Fifo8 *recv_fifo; + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (!(ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, MODE_EN) == 2)) { + return; + } + recv_fifo = &s->rx_fifo_g; + } else { + if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { + return; + } + recv_fifo = &s->rx_fifo; + } + while (recv_fifo->num >= 4 + && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) + { + size_t ret; + uint32_t num; + const void *rxd = pop_buf(recv_fifo, 4, &num); + + memcpy(rq->dma_buf, rxd, num); + + ret = stream_push(rq->dma, rq->dma_buf, 4); + assert(ret == 4); + xilinx_spips_check_flush(s); + } +} + static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, unsigned size) { @@ -556,6 +824,23 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret <<= 8 * shortfall; } DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_check_flush(s); + xilinx_spips_update_ixr(s); + return ret; + case R_GQSPI_RXD: + if (fifo8_is_empty(&s->rx_fifo_g)) { + qemu_log_mask(LOG_GUEST_ERROR, "Read from empty GQSPI RX FIFO\n"); + return 0; + } + memset(rx_buf, 0, sizeof(rx_buf)); + shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, s->num_txrx_bytes); + ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { + ret <<= 8 * shortfall; + } + xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } @@ -619,6 +904,49 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; + case R_GQSPI_CNFG: + mask = ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); + if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { + s->man_start_com_g = true; + } + break; + case R_GQSPI_GEN_FIFO: + if (!fifo32_is_full(&s->fifo_g)) { + fifo32_push(&s->fifo_g, value); + } + goto no_reg_update; + case R_GQSPI_TXD: + tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); + goto no_reg_update; + case R_GQSPI_FIFO_CTRL: + mask = 0; + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { + fifo32_reset(&s->fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { + fifo8_reset(&s->tx_fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { + fifo8_reset(&s->rx_fifo_g); + } + break; + case R_GQSPI_IDR: + s->regs[R_GQSPI_IMR] |= value; + goto no_reg_update; + case R_GQSPI_IER: + s->regs[R_GQSPI_IMR] &= ~value; + goto no_reg_update; + case R_GQSPI_ISR: + s->regs[R_GQSPI_ISR] &= ~value; + goto no_reg_update; + case R_GQSPI_IMR: + case R_GQSPI_RXD: + case R_GQSPI_GF_SNAPSHOT: + case R_GQSPI_MOD_ID: + mask = 0; + break; } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: @@ -662,6 +990,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { fifo8_reset(&s->rx_fifo); } + if (object_dynamic_cast(OBJECT(s), TYPE_XLNX_ZYNQMP_QSPIPS)) { + xlnx_zynqmp_qspips_notify(s); + } } static const MemoryRegionOps qspips_ops = { @@ -825,6 +1156,9 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); + fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); + fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); + fifo32_create(&s->fifo_g, 32); } static void xilinx_qspips_realize(DeviceState *dev, Error **errp) @@ -856,6 +1190,17 @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp) } } +static void xlnx_zynqmp_qspips_init(Object *obj) +{ + XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, + (Object **)&rq->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + NULL); +} + static int xilinx_spips_post_load(void *opaque, int version_id) { xilinx_spips_update_ixr((XilinxSPIPS *)opaque); @@ -936,10 +1281,18 @@ static const TypeInfo xilinx_qspips_info = { .class_init = xilinx_qspips_class_init, }; +static const TypeInfo xlnx_zynqmp_qspips_info = { + .name = TYPE_XLNX_ZYNQMP_QSPIPS, + .parent = TYPE_XILINX_QSPIPS, + .instance_size = sizeof(XlnxZynqMPQSPIPS), + .instance_init = xlnx_zynqmp_qspips_init, +}; + static void xilinx_spips_register_types(void) { type_register_static(&xilinx_spips_info); type_register_static(&xilinx_qspips_info); + type_register_static(&xlnx_zynqmp_qspips_info); } type_init(xilinx_spips_register_types) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index ad2175a..35f6a6f 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -26,11 +26,12 @@ #define XILINX_SPIPS_H #include "hw/ssi/ssi.h" -#include "qemu/fifo8.h" +#include "qemu/fifo32.h" +#include "hw/stream.h" typedef struct XilinxSPIPS XilinxSPIPS; -#define XLNX_SPIPS_R_MAX (0x100 / 4) +#define XLNX_SPIPS_R_MAX 0x200 /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 @@ -71,6 +72,18 @@ struct XilinxSPIPS { Fifo8 rx_fifo; Fifo8 tx_fifo; + /* GQSPI has seperate tx/rx fifos */ + Fifo8 rx_fifo_g; + Fifo8 tx_fifo_g; + Fifo32 fifo_g; + /* + * at the end of each generic command, misaligned extra bytes are discard + * or padded to tx and rx respectively to round it out (and avoid need for + * individual byte access. Since we use byte fifos, keep track of the + * alignment WRT to word access. + */ + uint8_t rx_fifo_g_align; + uint8_t tx_fifo_g_align; uint8_t num_txrx_bytes; uint32_t rx_discard; @@ -78,6 +91,7 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; bool man_start_com; + bool man_start_com_g; }; typedef struct { @@ -89,6 +103,13 @@ typedef struct { bool mmio_execution_enabled; } XilinxQSPIPS; +typedef struct { + XilinxQSPIPS parent_obj; + + StreamSlave *dma; + uint8_t dma_buf[4]; +} XlnxZynqMPQSPIPS; + typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; @@ -100,6 +121,7 @@ typedef struct XilinxSPIPSClass { #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" +#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) @@ -111,4 +133,7 @@ typedef struct XilinxSPIPSClass { #define XILINX_QSPIPS(obj) \ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) +#define XLNX_ZYNQMP_QSPIPS(obj) \ + OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS) + #endif /* XILINX_SPIPS_H */ From patchwork Sun Oct 29 10:13:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 831705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="th4uT52S"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yPtpd0d91z9t0F for ; Sun, 29 Oct 2017 21:17:45 +1100 (AEDT) Received: from localhost ([::1]:35471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kf1-0000kI-3a for incoming@patchwork.ozlabs.org; Sun, 29 Oct 2017 06:17:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e8kbY-0006h0-Rm for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e8kbX-0007vy-IE for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:08 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:50901) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e8kbX-0007vV-6q for qemu-devel@nongnu.org; Sun, 29 Oct 2017 06:14:07 -0400 Received: by mail-lf0-x244.google.com with SMTP id a132so11642131lfa.7 for ; Sun, 29 Oct 2017 03:14:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ddW3SArNvvFjjs495M1gpTHxygjfvu190VgkTuLQzkU=; b=th4uT52S3Dis2XFnd+QH4dKbM9LQYmTZqjOIEVgwN1SRGjKrHjHYne5Za/cEIZPrPd Z9nYv5tyV113OZk/OPeRQ7o2iw6xmGWlGmHRCxlp25n1vuFvdoZBBHlG8b+rE0YxJwi2 /8p2toyI/lUv7sBHP4BKwArakI3vq8UtS0ci+tc8ECDkoO1gDI97wk3yrLELOKgDoLxa yr2HbSHPSm/lS+cJhkzyw7ZXGjqnTv49AnKiRhtZmziJpyHtKv7wLP+vD9yMbyovOo05 PDg+CMsOwRTigaj5ZVKMWGMNU354ni9WZo81m6jf1J8CbH5GtU/i9BOlakIhHYZrjuxB 88Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ddW3SArNvvFjjs495M1gpTHxygjfvu190VgkTuLQzkU=; b=Fal58jo1Z3Ls1/1EWn0Z5yf9PhaieWSicVKuXJFaXpZPWzGWCgNFb/lFLYM0YpoSSF mYYWKXyUan8mWKTxFt/GHmF7SBmczqqQdxQPiD9AynBshZLxvZU9KieIQUfH2oSniv7c 1Y98Itwb05Im6uugmYNqBRYULCrJY7xlVZ5eJ3H2yJ3U7YAHhyuHVWKWetAp0Sniyngy T2hc1tSL6kLgJHuEImDHTQL0TvC2FA5p7QmePrv88emOBYbdPNdj0Ro88R43zxRhf/PC LS1FKdSVjAk8Z9qqzgrSyPBw72f86rpePVeihuQy8If6/LIa3URSnwGNJDbdAjmbQeWp QUEw== X-Gm-Message-State: AMCzsaXQVyL/uiSV4ecoRPNeQdAtIXxx/0eSgFN5f9F31xR1oSy8nZfR ZQ0ecjbL7H9YSrcF6v0SWauAuA== X-Google-Smtp-Source: ABhQp+R0wdm2Kx7ldmebWxOcohmzRAUmzHgG6JkUFoC4S0dYmVvO9ixoYh+Onr5snkGFROMNKSu68w== X-Received: by 10.46.33.86 with SMTP id h83mr2335880ljh.193.1509272045711; Sun, 29 Oct 2017 03:14:05 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id v62sm2819800lje.39.2017.10.29.03.14.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 03:14:04 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sun, 29 Oct 2017 11:13:43 +0100 Message-Id: <20171029101343.15544-14-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171029101343.15544-1-frasse.iglesias@gmail.com> References: <20171029101343.15544-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 Subject: [Qemu-devel] [PATCH v5 13/13] xlnx-zcu102: Add support for the ZynqMP QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis --- hw/arm/xlnx-zcu102.c | 23 +++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 5 +++++ 3 files changed, 54 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..7d61972 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -150,6 +150,29 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); } + for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { + SSIBus *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo = drive_get_next(IF_MTD); + int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; + gchar *bus_name = g_strdup_printf("qspi%d", bus); + + spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name); + g_free(bus_name); + + flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11"); + if (dinfo) { + qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_init_nofail(flash_dev); + + cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); + } + /* TODO create and connect IDE devices for ide_drive_get() */ xlnx_zcu102_binfo.ram_size = ram_size; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d4b6560..46ac45d 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -40,6 +40,10 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 +#define QSPI_ADDR 0xff0f0000 +#define LQSPI_ADDR 0xc0000000 +#define QSPI_IRQ 15 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 @@ -169,6 +173,9 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } + object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); + qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); + object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); @@ -405,6 +412,25 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) g_free(bus_name); } + object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); + + for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { + gchar *bus_name; + gchar *target_bus; + + /* Alias controller SPI bus to the SoC itself */ + bus_name = g_strdup_printf("qspi%d", i); + target_bus = g_strdup_printf("spi%d", i); + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->qspi), target_bus, + &error_abort); + g_free(bus_name); + g_free(target_bus); + } + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a..3e6fb9b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma;