From patchwork Wed Oct 25 10:52:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Philippe Bergheaud X-Patchwork-Id: 830231 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yMRp64HZ7z9sNx for ; Wed, 25 Oct 2017 21:53:50 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yMRp62z4czDr67 for ; Wed, 25 Oct 2017 21:53:50 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=felix@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yMRmh0nxCzDqkr for ; Wed, 25 Oct 2017 21:52:35 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v9PAmfYZ054258 for ; Wed, 25 Oct 2017 06:52:32 -0400 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0b-001b2d01.pphosted.com with ESMTP id 2dtqyb45hk-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 25 Oct 2017 06:52:32 -0400 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 25 Oct 2017 11:52:28 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v9PAqRIb27525324; Wed, 25 Oct 2017 10:52:27 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D657911C05E; Wed, 25 Oct 2017 11:47:41 +0100 (BST) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C246011C050; Wed, 25 Oct 2017 11:47:41 +0100 (BST) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 25 Oct 2017 11:47:41 +0100 (BST) Received: from w541.lab.toulouse-stg.fr.ibm.com (t42p.lab.toulouse-stg.fr.ibm.com [9.101.4.37]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 0FD8F220076; Wed, 25 Oct 2017 12:52:27 +0200 (CEST) From: Philippe Bergheaud To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH] powerpc/powernv: Enable tunneled operations Date: Wed, 25 Oct 2017 12:52:15 +0200 X-Mailer: git-send-email 2.14.2 X-TM-AS-GCONF: 00 x-cbid: 17102510-0016-0000-0000-000004F9AF1D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17102510-0017-0000-0000-000028352441 Message-Id: <20171025105215.19547-1-felix@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-25_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710250149 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Philippe Bergheaud , clombard@linux.vnet.ibm.com, fbarrat@linux.vnet.ibm.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" P9 supports PCI tunneled operations (atomics and as_notify). This patch adds support for tunneled operations on powernv, by adding a new API to be called by drivers: pnv_pci_get_tunnel_ind() -- tell driver the 16-bit ASN indication set by kernel. pnv_pci_set_tunnel_bar() -- tell kernel the Tunnel BAR address mask used by driver. These functions use four new OPAL calls, as PBCQ and PHB configurations are done by skiboot. Signed-off-by: Philippe Bergheaud Acked-by:  Christophe Lombard --- This patch depends on the following skiboot prerequisites: https://patchwork.ozlabs.org/patch/829294/ [1/2] phb4: set PHB CMPM registers for tunneled operations https://patchwork.ozlabs.org/patch/829293/ [2/2] phb4: set PBCQ Tunnel BAR for tunneled operations arch/powerpc/include/asm/opal-api.h | 13 +++- arch/powerpc/include/asm/opal.h | 4 ++ arch/powerpc/include/asm/pnv-pci.h | 3 + arch/powerpc/platforms/powernv/opal-wrappers.S | 4 ++ arch/powerpc/platforms/powernv/pci.c | 92 ++++++++++++++++++++++++++ 5 files changed, 115 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h index 450a60b81d2a..607d94d8d863 100644 --- a/arch/powerpc/include/asm/opal-api.h +++ b/arch/powerpc/include/asm/opal-api.h @@ -200,7 +200,11 @@ #define OPAL_SET_POWER_SHIFT_RATIO 155 #define OPAL_SENSOR_GROUP_CLEAR 156 #define OPAL_PCI_SET_P2P 157 -#define OPAL_LAST 157 +#define OPAL_PCI_GET_PHB_CMPM 158 +#define OPAL_PCI_SET_PHB_CMPM 159 +#define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 160 +#define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 161 +#define OPAL_LAST 161 /* Device tree flags */ @@ -1106,6 +1110,13 @@ enum { #define OPAL_PCI_P2P_LOAD 0x2 #define OPAL_PCI_P2P_STORE 0x4 +/* PHB Compare/Mask registers */ +enum { + OPAL_PHB_ASN_CMPM = 0, + OPAL_PHB_CAPI_CMPM = 1, + OPAL_PHB_PBL_NBW_CMPM = 2, +}; + #endif /* __ASSEMBLY__ */ #endif /* __OPAL_API_H */ diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h index 726c23304a57..556c16d60930 100644 --- a/arch/powerpc/include/asm/opal.h +++ b/arch/powerpc/include/asm/opal.h @@ -198,6 +198,10 @@ int64_t opal_unregister_dump_region(uint32_t id); int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag); int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number); +int64_t opal_pci_get_phb_cmpm(uint64_t phb_id, uint64_t phb_reg, uint64_t *ind); +int64_t opal_pci_set_phb_cmpm(uint64_t phb_id, uint64_t phb_reg, uint64_t ind); +int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr); +int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr); int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg, uint64_t msg_len); int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg, diff --git a/arch/powerpc/include/asm/pnv-pci.h b/arch/powerpc/include/asm/pnv-pci.h index 3e5cf251ad9a..73b320732fff 100644 --- a/arch/powerpc/include/asm/pnv-pci.h +++ b/arch/powerpc/include/asm/pnv-pci.h @@ -28,6 +28,9 @@ extern int pnv_pci_set_power_state(uint64_t id, uint8_t state, struct opal_msg *msg); extern int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target, u64 desc); +extern int pnv_pci_get_tunnel_ind(struct pci_dev *dev, uint64_t *ind); +extern int pnv_pci_set_tunnel_bar(struct pci_dev *dev, uint64_t addr, + int enable); int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode); int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S index 8c1ede2d3f7e..9de8cd43380f 100644 --- a/arch/powerpc/platforms/powernv/opal-wrappers.S +++ b/arch/powerpc/platforms/powernv/opal-wrappers.S @@ -319,3 +319,7 @@ OPAL_CALL(opal_set_powercap, OPAL_SET_POWERCAP); OPAL_CALL(opal_get_power_shift_ratio, OPAL_GET_POWER_SHIFT_RATIO); OPAL_CALL(opal_set_power_shift_ratio, OPAL_SET_POWER_SHIFT_RATIO); OPAL_CALL(opal_sensor_group_clear, OPAL_SENSOR_GROUP_CLEAR); +OPAL_CALL(opal_pci_get_phb_cmpm, OPAL_PCI_GET_PHB_CMPM); +OPAL_CALL(opal_pci_set_phb_cmpm, OPAL_PCI_SET_PHB_CMPM); +OPAL_CALL(opal_pci_get_pbcq_tunnel_bar, OPAL_PCI_GET_PBCQ_TUNNEL_BAR); +OPAL_CALL(opal_pci_set_pbcq_tunnel_bar, OPAL_PCI_SET_PBCQ_TUNNEL_BAR); diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c index 5422f4a6317c..26230a45e24e 100644 --- a/arch/powerpc/platforms/powernv/pci.c +++ b/arch/powerpc/platforms/powernv/pci.c @@ -38,6 +38,7 @@ #include "pci.h" static DEFINE_MUTEX(p2p_mutex); +static DEFINE_MUTEX(tunnel_mutex); int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id) { @@ -1092,6 +1093,97 @@ int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target, u64 desc) } EXPORT_SYMBOL_GPL(pnv_pci_set_p2p); +int pnv_pci_get_tunnel_ind(struct pci_dev *dev, u64 *ind) +{ + __be64 val; + struct pci_controller *hose; + struct pnv_phb *phb; + u64 asnind; + int rc; + + if (!opal_check_token(OPAL_PCI_GET_PHB_CMPM)) + return -ENXIO; + if (!opal_check_token(OPAL_PCI_SET_PHB_CMPM)) + return -ENXIO; + + hose = pci_bus_to_host(dev->bus); + phb = hose->private_data; + + mutex_lock(&tunnel_mutex); + rc = opal_pci_get_phb_cmpm(phb->opal_id, OPAL_PHB_ASN_CMPM, &val); + if (rc != OPAL_SUCCESS) { + rc = -EIO; + goto out; + } + asnind = be64_to_cpu(val); + if (asnind) + goto done; + + /* Hard-coded value for now */ + asnind = 0x0400; + rc = opal_pci_set_phb_cmpm(phb->opal_id, OPAL_PHB_ASN_CMPM, asnind); + rc = opal_error_code(rc); + if (rc) + goto out; +done: + *ind = asnind; +out: + mutex_unlock(&tunnel_mutex); + return rc; +} +EXPORT_SYMBOL_GPL(pnv_pci_get_tunnel_ind); + +int pnv_pci_set_tunnel_bar(struct pci_dev *dev, u64 addr, int enable) +{ + __be64 val; + struct pci_controller *hose; + struct pnv_phb *phb; + u64 tunnel_bar; + int rc; + + if (!opal_check_token(OPAL_PCI_GET_PBCQ_TUNNEL_BAR)) + return -ENXIO; + if (!opal_check_token(OPAL_PCI_SET_PBCQ_TUNNEL_BAR)) + return -ENXIO; + + hose = pci_bus_to_host(dev->bus); + phb = hose->private_data; + + mutex_lock(&tunnel_mutex); + rc = opal_pci_get_pbcq_tunnel_bar(phb->opal_id, &val); + if (rc != OPAL_SUCCESS) { + rc = -EIO; + goto out; + } + tunnel_bar = be64_to_cpu(val); + if (enable) { + /* + * Only one device per PHB can use atomics. + * Our policy is first-come, first-served. + */ + if (tunnel_bar) { + rc = -EBUSY; + goto out; + } + } else { + /* + * The device that owns atomics and wants to release them + * must reuse the same address, and reset the enable bit. + */ + if (tunnel_bar != addr) { + rc = -EPERM; + goto out; + } + addr = 0x0ull; + } + rc = opal_pci_set_pbcq_tunnel_bar(phb->opal_id, addr); + rc = opal_error_code(rc); +out: + mutex_unlock(&tunnel_mutex); + return rc; +} +EXPORT_SYMBOL_GPL(pnv_pci_set_tunnel_bar); + void pnv_pci_shutdown(void) { struct pci_controller *hose;