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[SRU,O,5/5] perf/x86/intel/uncore: Use D0:F0 as a default device

Message ID 20240924092446.26884-6-aaron.ma@canonical.com
State New
Headers show
Series uncore: Add ARL and LNL support on 6.11 | expand

Commit Message

Aaron Ma Sept. 24, 2024, 9:24 a.m. UTC 
From: Zhenyu Wang <zhenyuw@linux.intel.com>

BugLink: https://bugs.launchpad.net/bugs/2081810

Some uncore PMON registers are located in the MMIO space of the Host
Bridge and DRAM Controller device, which is located at D0:F0 for
Tiger Lake and later client generation.

Use D0:F0 as a default device. So it doesn't need to keep adding the
complete Device ID list for each generation anymore.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Link: https://lore.kernel.org/r/20240731141353.759643-5-kan.liang@linux.intel.com
(cherry picked from commit aaad0e2aa50723969f96b690f72e2f4aefa433f2)
Signed-off-by: Aaron Ma <aaron.ma@canonical.com>
---
 arch/x86/events/intel/uncore_snb.c | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index f7402bd4da6e..3934e1e4e3b1 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -1504,6 +1504,10 @@  static struct pci_dev *tgl_uncore_get_mc_dev(void)
 		ids++;
 	}
 
+	/* Just try to grab 00:00.0 device */
+	if (!mc_dev)
+		mc_dev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
+
 	return mc_dev;
 }