diff mbox series

[V3,01/10] clk: imx6q: Properly handle imx6qp ECSPI clk_sels

Message ID 20250318233849.587520-2-aford173@gmail.com
State Accepted
Delegated to: Fabio Estevam
Headers show
Series clk: imx: Use Clock framework to register UART clocks | expand

Commit Message

Adam Ford March 18, 2025, 11:38 p.m. UTC 
The ECSPI clock has the ability to select between pll3_60m and
osc on the imx6qp, where it's fixed on other variants.  Fix this
by adding using a helper function to determine SoC variant and
register the clock accordingly.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx6q.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

V3:  No change 
V2:  Fix the name "ECSPI" and elimiate helper function by
     directly calling of_machine_is_compatible.

Comments

Fabio Estevam March 19, 2025, 4:14 p.m. UTC | #1 
On Tue, Mar 18, 2025 at 8:42 PM Adam Ford <aford173@gmail.com> wrote:

> +       if (of_machine_is_compatible("fsl,imx6qp")

Missing closing parenthesis.

> -       clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
> -              imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
> +       if (of_machine_is_compatible("fsl,imx6qp")

Same here.
Adam Ford March 19, 2025, 4:39 p.m. UTC | #2 
On Wed, Mar 19, 2025 at 11:15 AM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Tue, Mar 18, 2025 at 8:42 PM Adam Ford <aford173@gmail.com> wrote:
>
> > +       if (of_machine_is_compatible("fsl,imx6qp")
>
> Missing closing parenthesis.
>
> > -       clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
> > -              imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
> > +       if (of_machine_is_compatible("fsl,imx6qp")
>
> Same here.

Sorry about all the noise.

I think I forgot to type 'git add' before the "git commit --amend" so
the fix didn't get applied, but because the same file was shown in the
commit message, it looked like the fix was in place.  I'll have to
confirm when I get back to my build machine.

I'll manually build a few more mx6 platforms and try to spend some
more time trying to figure out the CI/CD tools.

adam
Fabio Estevam March 19, 2025, 5:27 p.m. UTC | #3 
On Wed, Mar 19, 2025 at 1:39 PM Adam Ford <aford173@gmail.com> wrote:

> Sorry about all the noise.
>
> I think I forgot to type 'git add' before the "git commit --amend" so
> the fix didn't get applied, but because the same file was shown in the
> commit message, it looked like the fix was in place.  I'll have to
> confirm when I get back to my build machine.
>
> I'll manually build a few more mx6 platforms and try to spend some
> more time trying to figure out the CI/CD tools.

I have manually fixed patches 1 and 2 and now CI is happy with the series.

No need to resend it.
Adam Ford March 19, 2025, 5:29 p.m. UTC | #4 
On Wed, Mar 19, 2025 at 12:27 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Wed, Mar 19, 2025 at 1:39 PM Adam Ford <aford173@gmail.com> wrote:
>
> > Sorry about all the noise.
> >
> > I think I forgot to type 'git add' before the "git commit --amend" so
> > the fix didn't get applied, but because the same file was shown in the
> > commit message, it looked like the fix was in place.  I'll have to
> > confirm when I get back to my build machine.
> >
> > I'll manually build a few more mx6 platforms and try to spend some
> > more time trying to figure out the CI/CD tools.
>
> I have manually fixed patches 1 and 2 and now CI is happy with the series.
>
> No need to resend it.

I am sorry you had to do that.  :-(

Thanks for help.

adam
Fabio Estevam March 21, 2025, 12:31 p.m. UTC | #5 
On Wed, Mar 19, 2025 at 2:27 PM Fabio Estevam <festevam@gmail.com> wrote:

> I have manually fixed patches 1 and 2 and now CI is happy with the series.
>
> No need to resend it.

Applied the series to u-boot-imx/next, thanks.
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index df9f0285e1e..15ad0c9ac06 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -35,6 +35,7 @@  static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *const periph_sels[]	= { "periph_pre", "periph_clk2", };
 static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
 					       "pll2_pfd0_352m", "pll2_198m", };
+static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
 
 static int imx6q_clk_probe(struct udevice *dev)
 {
@@ -78,6 +79,11 @@  static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 
+	if (of_machine_is_compatible("fsl,imx6qp")
+		clk_dm(IMX6QDL_CLK_ECSPI_SEL,
+		       imx_clk_mux("ecspi_sel",	base + 0x38, 18, 1, ecspi_sels,
+				   ARRAY_SIZE(ecspi_sels)));
+
 	clk_dm(IMX6QDL_CLK_USDHC1_PODF,
 	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
@@ -91,8 +97,12 @@  static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_divider("usdhc4_podf", "usdhc4_sel",
 			       base + 0x24, 22, 3));
 
-	clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
-	       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+	if (of_machine_is_compatible("fsl,imx6qp")
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
+	else
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
 
 	clk_dm(IMX6QDL_CLK_ECSPI1,
 	       imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));