| Message ID | 20250123083626.1035262-1-s-k6@ti.com |
|---|---|
| State | Accepted |
| Commit | 5a42996c4909f2ec6c26c1ad7eebf23eefe9d02e |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | ram: k3-ddrss: Set SDRAM_IDX using device private data, ddr_ram_size | expand |
Hi Santhosh On 23-Jan-25 2:06 PM, Santhosh Kumar K wrote: > The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits > minus 16 that are used to determine the mask used to detect memory > rollover and prevent aliasing and false coherency issues. > > Set SDRAM_IDX using the device private data, ddr_ram_size for K3 family > of SoCs. > > Signed-off-by: Santhosh Kumar K <s-k6@ti.com> > --- > > Tested on AM64x, AM62Ax, AM62Px. > Logs: https://gist.github.com/santhosh21/6dcdeb9a118c13732f858a1baca7dc4c > > --- > drivers/ram/k3-ddrss/k3-ddrss.c | 32 +++++++++++++++++++++++++------- > 1 file changed, 25 insertions(+), 7 deletions(-) > > diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c > index 05ea61bbfe9a..ff87faf6a224 100644 > --- a/drivers/ram/k3-ddrss/k3-ddrss.c > +++ b/drivers/ram/k3-ddrss/k3-ddrss.c > @@ -33,6 +33,12 @@ > #define DDRSS_V2A_CTL_REG 0x0020 > #define DDRSS_ECC_CTRL_REG 0x0120 > > +#define DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(x) ((ilog2(x) - 16) << 5) > +#define DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK (~(0x1F << 0x5)) > +#define DDRSS_V2A_CTL_REG_REGION_IDX_MASK (~(0X1F)) > +#define DDRSS_V2A_CTL_REG_REGION_IDX_DEFAULT 0xF > + > +#define DDRSS_ECC_CTRL_REG_DEFAULT 0x0 > #define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0) > #define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1) > #define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2) > @@ -711,6 +717,22 @@ static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss) > ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank]; > } > > +static void k3_ddrss_ddr_reg_init(struct k3_ddrss_desc *ddrss) > +{ > + u32 v2a_ctl_reg, sdram_idx; > + > + sdram_idx = DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(ddrss->ddr_ram_size); > + v2a_ctl_reg = readl(ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); > + v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK) | sdram_idx; > + > + if (IS_ENABLED(CONFIG_SOC_K3_AM642)) > + v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_REGION_IDX_MASK) | > + DDRSS_V2A_CTL_REG_REGION_IDX_DEFAULT; > + > + writel(v2a_ctl_reg, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); > + writel(DDRSS_ECC_CTRL_REG_DEFAULT, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); > +} > + > static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) > { > fdtdec_setup_mem_size_base_lowest(); > @@ -769,11 +791,9 @@ static int k3_ddrss_probe(struct udevice *dev) > if (ret) > return ret; > > -#ifdef CONFIG_K3_AM64_DDRSS > - /* AM64x supports only up to 2 GB SDRAM */ > - writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); > - writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); > -#endif > + k3_ddrss_ddr_bank_base_size_calc(ddrss); > + > + k3_ddrss_ddr_reg_init(ddrss); > > ddrss->driverdt = lpddr4_getinstance(); > > @@ -787,8 +807,6 @@ static int k3_ddrss_probe(struct udevice *dev) > > k3_lpddr4_start(ddrss); > > - k3_ddrss_ddr_bank_base_size_calc(ddrss); > - > if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) { > if (!ddrss->ddrss_ss_cfg) { > printf("%s: ss_cfg is required if ecc is enabled but not provided.", Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Also sanity tested on J721E, J721S2 and J784S4 boards.
On Thu, 23 Jan 2025 14:06:26 +0530, Santhosh Kumar K wrote: > The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits > minus 16 that are used to determine the mask used to detect memory > rollover and prevent aliasing and false coherency issues. > > Set SDRAM_IDX using the device private data, ddr_ram_size for K3 family > of SoCs. > > [...] Applied to u-boot/master, thanks!
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 05ea61bbfe9a..ff87faf6a224 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -33,6 +33,12 @@ #define DDRSS_V2A_CTL_REG 0x0020 #define DDRSS_ECC_CTRL_REG 0x0120 +#define DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(x) ((ilog2(x) - 16) << 5) +#define DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK (~(0x1F << 0x5)) +#define DDRSS_V2A_CTL_REG_REGION_IDX_MASK (~(0X1F)) +#define DDRSS_V2A_CTL_REG_REGION_IDX_DEFAULT 0xF + +#define DDRSS_ECC_CTRL_REG_DEFAULT 0x0 #define DDRSS_ECC_CTRL_REG_ECC_EN BIT(0) #define DDRSS_ECC_CTRL_REG_RMW_EN BIT(1) #define DDRSS_ECC_CTRL_REG_ECC_CK BIT(2) @@ -711,6 +717,22 @@ static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss) ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank]; } +static void k3_ddrss_ddr_reg_init(struct k3_ddrss_desc *ddrss) +{ + u32 v2a_ctl_reg, sdram_idx; + + sdram_idx = DDRSS_V2A_CTL_REG_SDRAM_IDX_CALC(ddrss->ddr_ram_size); + v2a_ctl_reg = readl(ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); + v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_SDRAM_IDX_MASK) | sdram_idx; + + if (IS_ENABLED(CONFIG_SOC_K3_AM642)) + v2a_ctl_reg = (v2a_ctl_reg & DDRSS_V2A_CTL_REG_REGION_IDX_MASK) | + DDRSS_V2A_CTL_REG_REGION_IDX_DEFAULT; + + writel(v2a_ctl_reg, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); + writel(DDRSS_ECC_CTRL_REG_DEFAULT, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); +} + static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest(); @@ -769,11 +791,9 @@ static int k3_ddrss_probe(struct udevice *dev) if (ret) return ret; -#ifdef CONFIG_K3_AM64_DDRSS - /* AM64x supports only up to 2 GB SDRAM */ - writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_CTL_REG); - writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG); -#endif + k3_ddrss_ddr_bank_base_size_calc(ddrss); + + k3_ddrss_ddr_reg_init(ddrss); ddrss->driverdt = lpddr4_getinstance(); @@ -787,8 +807,6 @@ static int k3_ddrss_probe(struct udevice *dev) k3_lpddr4_start(ddrss); - k3_ddrss_ddr_bank_base_size_calc(ddrss); - if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.",
The SDRAM_IDX in DDRSS_V2A_CTL_REG describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Set SDRAM_IDX using the device private data, ddr_ram_size for K3 family of SoCs. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> --- Tested on AM64x, AM62Ax, AM62Px. Logs: https://gist.github.com/santhosh21/6dcdeb9a118c13732f858a1baca7dc4c --- drivers/ram/k3-ddrss/k3-ddrss.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-)