diff mbox series

mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes

Message ID 20241122092619.1376234-1-venkatesh.abbarapu@amd.com
State Changes Requested
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes | expand

Commit Message

Venkatesh Yadav Abbarapu Nov. 22, 2024, 9:26 a.m. UTC 
Enable mt35xu512aba_fixups for all mt35 series flashes to work
in DTR mode, and return after nor->fixups is updated, otherwise
it will get overwritten with macronix_octal_fixups.
This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU
is enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.

Additionally, a new flag, "SPI_XFER_SET_DDR", has been introduced
to instruct the OSPI controller driver to switch to DDR mode.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
---
 drivers/mtd/spi/spi-nor-core.c | 8 +++++++-
 include/spi.h                  | 1 +
 2 files changed, 8 insertions(+), 1 deletion(-)

Comments

Tudor Ambarus Nov. 25, 2024, 7:40 a.m. UTC | #1 
On 11/22/24 9:26 AM, Venkatesh Yadav Abbarapu wrote:
> Enable mt35xu512aba_fixups for all mt35 series flashes to work
> in DTR mode, and return after nor->fixups is updated, otherwise
> it will get overwritten with macronix_octal_fixups.
> This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU
> is enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.
> 
> Additionally, a new flag, "SPI_XFER_SET_DDR", has been introduced
> to instruct the OSPI controller driver to switch to DDR mode.

Can you use the dtr fields from `struct spi_mem_op` instead?
Prasanth Babu Mantena Nov. 25, 2024, 8:49 a.m. UTC | #2 
On 14:56, Venkatesh Yadav Abbarapu wrote:
Hi Venkatesh, 
> Enable mt35xu512aba_fixups for all mt35 series flashes to work
> in DTR mode, and return after nor->fixups is updated, otherwise
> it will get overwritten with macronix_octal_fixups.
> This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU
> is enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.
> 
> Additionally, a new flag, "SPI_XFER_SET_DDR", has been introduced
> to instruct the OSPI controller driver to switch to DDR mode.
> 
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
> ---
>  drivers/mtd/spi/spi-nor-core.c | 8 +++++++-
>  include/spi.h                  | 1 +
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index ec841fb13b..8d201433d5 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -4073,6 +4073,7 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
>  	if (ret)
>  		return ret;
>  
> +	nor->spi->flags |= SPI_XFER_SET_DDR;
>  	buf = SPINOR_MT_OCT_DTR;
>  	op = (struct spi_mem_op)
>  		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
> @@ -4404,8 +4405,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)
>  #endif
>  
>  #ifdef CONFIG_SPI_FLASH_MT35XU
> -	if (!strcmp(nor->info->name, "mt35xu512aba"))
> +	if (!strcmp(nor->info->name, "mt35xu512aba") ||
> +	    !strcmp(nor->info->name, "mt35xl512aba") ||
> +	    !strcmp(nor->info->name, "mt35xu01g") ||
> +	    !strcmp(nor->info->name, "mt35xu02g")) {
>  		nor->fixups = &mt35xu512aba_fixups;
> +		return;
> +	}
>  #endif
>  
>  #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> diff --git a/include/spi.h b/include/spi.h
> index 6944773b59..d7fef36662 100644
> --- a/include/spi.h
> +++ b/include/spi.h
> @@ -164,6 +164,7 @@ struct spi_slave {
>  #define SPI_XFER_U_PAGE		BIT(4)
>  #define SPI_XFER_STACKED	BIT(5)
>  #define SPI_XFER_LOWER		BIT(6)
> +#define SPI_XFER_SET_DDR	BIT(7)

Are we using this anywhere in the Controller driver ? What is the
significance of this flag, when we can send the DDR info through
the ops.

>  
>  	/*
>  	 * Flag indicating that the spi-controller has multi chip select
> -- 
> 2.25.1
> 
>
Venkatesh Yadav Abbarapu Nov. 25, 2024, 9:12 a.m. UTC | #3 
Hi Prasanth,

> -----Original Message-----
> From: Prasanth Mantena <p-mantena@ti.com>
> Sent: Monday, November 25, 2024 2:19 PM
> To: Abbarapu, Venkatesh <venkatesh.abbarapu@amd.com>
> Cc: u-boot@lists.denx.de; j-humphreys@ti.com; Simek, Michal
> <michal.simek@amd.com>; jagan@amarulasolutions.com; vigneshr@ti.com; u-
> kumar1@ti.com; trini@konsulko.com; seanga2@gmail.com;
> caleb.connolly@linaro.org; sjg@chromium.org; william.zhang@broadcom.com;
> stefan_b@posteo.net; quentin.schulz@cherry.de; tudor.ambarus@linaro.org;
> Takahiro.Kuwano@infineon.com; git (AMD-Xilinx) <git@amd.com>; Ashok Reddy
> Soma <ashok.reddy.soma@amd.com>
> Subject: Re: [PATCH] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx
> flashes
> 
> On 14:56, Venkatesh Yadav Abbarapu wrote:
> Hi Venkatesh,
> > Enable mt35xu512aba_fixups for all mt35 series flashes to work in DTR
> > mode, and return after nor->fixups is updated, otherwise it will get
> > overwritten with macronix_octal_fixups.
> > This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU is
> > enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.
> >
> > Additionally, a new flag, "SPI_XFER_SET_DDR", has been introduced to
> > instruct the OSPI controller driver to switch to DDR mode.
> >
> > Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
> > Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
> > ---
> >  drivers/mtd/spi/spi-nor-core.c | 8 +++++++-
> >  include/spi.h                  | 1 +
> >  2 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c
> > b/drivers/mtd/spi/spi-nor-core.c index ec841fb13b..8d201433d5 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -4073,6 +4073,7 @@ static int spi_nor_micron_octal_dtr_enable(struct
> spi_nor *nor)
> >  	if (ret)
> >  		return ret;
> >
> > +	nor->spi->flags |= SPI_XFER_SET_DDR;
> >  	buf = SPINOR_MT_OCT_DTR;
> >  	op = (struct spi_mem_op)
> >
> 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
> @@ -4404,8
> > +4405,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)  #endif
> >
> >  #ifdef CONFIG_SPI_FLASH_MT35XU
> > -	if (!strcmp(nor->info->name, "mt35xu512aba"))
> > +	if (!strcmp(nor->info->name, "mt35xu512aba") ||
> > +	    !strcmp(nor->info->name, "mt35xl512aba") ||
> > +	    !strcmp(nor->info->name, "mt35xu01g") ||
> > +	    !strcmp(nor->info->name, "mt35xu02g")) {
> >  		nor->fixups = &mt35xu512aba_fixups;
> > +		return;
> > +	}
> >  #endif
> >
> >  #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > diff --git a/include/spi.h b/include/spi.h index
> > 6944773b59..d7fef36662 100644
> > --- a/include/spi.h
> > +++ b/include/spi.h
> > @@ -164,6 +164,7 @@ struct spi_slave {
> >  #define SPI_XFER_U_PAGE		BIT(4)
> >  #define SPI_XFER_STACKED	BIT(5)
> >  #define SPI_XFER_LOWER		BIT(6)
> > +#define SPI_XFER_SET_DDR	BIT(7)
> 
> Are we using this anywhere in the Controller driver ? What is the significance of this
> flag, when we can send the DDR info through the ops.
Yes...we will be checking this 
If (spi->flags & SPI_XFER_SET_DDR) && op->cmd.dtr) then 
	setup the DDR mode in controller driver.

I need to send the controller change series.

Thanks
Venkatesh
> 
> >
> >  	/*
> >  	 * Flag indicating that the spi-controller has multi chip select
> > --
> > 2.25.1
> >
> >
Prasanth Babu Mantena Nov. 26, 2024, 5:08 a.m. UTC | #4 
On 09:12, Abbarapu, Venkatesh wrote:
Hi Venkatesh,

> Hi Prasanth,
> 
> > -----Original Message-----
> > From: Prasanth Mantena <p-mantena@ti.com>
> > Sent: Monday, November 25, 2024 2:19 PM
> > To: Abbarapu, Venkatesh <venkatesh.abbarapu@amd.com>
> > Cc: u-boot@lists.denx.de; j-humphreys@ti.com; Simek, Michal
> > <michal.simek@amd.com>; jagan@amarulasolutions.com; vigneshr@ti.com; u-
> > kumar1@ti.com; trini@konsulko.com; seanga2@gmail.com;
> > caleb.connolly@linaro.org; sjg@chromium.org; william.zhang@broadcom.com;
> > stefan_b@posteo.net; quentin.schulz@cherry.de; tudor.ambarus@linaro.org;
> > Takahiro.Kuwano@infineon.com; git (AMD-Xilinx) <git@amd.com>; Ashok Reddy
> > Soma <ashok.reddy.soma@amd.com>
> > Subject: Re: [PATCH] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx
> > flashes
> > 
> > On 14:56, Venkatesh Yadav Abbarapu wrote:
> > Hi Venkatesh,
> > > Enable mt35xu512aba_fixups for all mt35 series flashes to work in DTR
> > > mode, and return after nor->fixups is updated, otherwise it will get
> > > overwritten with macronix_octal_fixups.
> > > This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU is
> > > enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.
> > >
> > > Additionally, a new flag, "SPI_XFER_SET_DDR", has been introduced to
> > > instruct the OSPI controller driver to switch to DDR mode.
> > >
> > > Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
> > > Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
> > > ---
> > >  drivers/mtd/spi/spi-nor-core.c | 8 +++++++-
> > >  include/spi.h                  | 1 +
> > >  2 files changed, 8 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mtd/spi/spi-nor-core.c
> > > b/drivers/mtd/spi/spi-nor-core.c index ec841fb13b..8d201433d5 100644
> > > --- a/drivers/mtd/spi/spi-nor-core.c
> > > +++ b/drivers/mtd/spi/spi-nor-core.c
> > > @@ -4073,6 +4073,7 @@ static int spi_nor_micron_octal_dtr_enable(struct
> > spi_nor *nor)
> > >  	if (ret)
> > >  		return ret;
> > >
> > > +	nor->spi->flags |= SPI_XFER_SET_DDR;
> > >  	buf = SPINOR_MT_OCT_DTR;
> > >  	op = (struct spi_mem_op)
> > >
> > 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
> > @@ -4404,8
> > > +4405,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)  #endif
> > >
> > >  #ifdef CONFIG_SPI_FLASH_MT35XU
> > > -	if (!strcmp(nor->info->name, "mt35xu512aba"))
> > > +	if (!strcmp(nor->info->name, "mt35xu512aba") ||
> > > +	    !strcmp(nor->info->name, "mt35xl512aba") ||
> > > +	    !strcmp(nor->info->name, "mt35xu01g") ||
> > > +	    !strcmp(nor->info->name, "mt35xu02g")) {
> > >  		nor->fixups = &mt35xu512aba_fixups;
> > > +		return;
> > > +	}
> > >  #endif
> > >
> > >  #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > > diff --git a/include/spi.h b/include/spi.h index
> > > 6944773b59..d7fef36662 100644
> > > --- a/include/spi.h
> > > +++ b/include/spi.h
> > > @@ -164,6 +164,7 @@ struct spi_slave {
> > >  #define SPI_XFER_U_PAGE		BIT(4)
> > >  #define SPI_XFER_STACKED	BIT(5)
> > >  #define SPI_XFER_LOWER		BIT(6)
> > > +#define SPI_XFER_SET_DDR	BIT(7)
> > 
> > Are we using this anywhere in the Controller driver ? What is the significance of this
> > flag, when we can send the DDR info through the ops.
> Yes...we will be checking this 
> If (spi->flags & SPI_XFER_SET_DDR) && op->cmd.dtr) then 
> 	setup the DDR mode in controller driver.

Is this change going to be for every read/write exec op or in some init
function. Current driver has this setup dtr mode on checking the opcode.
Curious to know, what does this extra flag bring something new to the driver.

Prasanth

> 
> I need to send the controller change series.
> 
> Thanks
> Venkatesh
> > 
> > >
> > >  	/*
> > >  	 * Flag indicating that the spi-controller has multi chip select
> > > --
> > > 2.25.1
> > >
> > >
Venkatesh Yadav Abbarapu Nov. 27, 2024, 3 a.m. UTC | #5 
Hi Prasanth,

> -----Original Message-----
> From: Prasanth Mantena <p-mantena@ti.com>
> Sent: Tuesday, November 26, 2024 10:38 AM
> To: Abbarapu, Venkatesh <venkatesh.abbarapu@amd.com>
> Cc: u-boot@lists.denx.de; j-humphreys@ti.com; Simek, Michal
> <michal.simek@amd.com>; jagan@amarulasolutions.com; vigneshr@ti.com; u-
> kumar1@ti.com; trini@konsulko.com; seanga2@gmail.com;
> caleb.connolly@linaro.org; sjg@chromium.org; william.zhang@broadcom.com;
> stefan_b@posteo.net; quentin.schulz@cherry.de; tudor.ambarus@linaro.org;
> Takahiro.Kuwano@infineon.com; git (AMD-Xilinx) <git@amd.com>; Ashok Reddy
> Soma <ashok.reddy.soma@amd.com>
> Subject: Re: [PATCH] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx
> flashes
> 
> On 09:12, Abbarapu, Venkatesh wrote:
> Hi Venkatesh,
> 
> > Hi Prasanth,
> >
> > > -----Original Message-----
> > > From: Prasanth Mantena <p-mantena@ti.com>
> > > Sent: Monday, November 25, 2024 2:19 PM
> > > To: Abbarapu, Venkatesh <venkatesh.abbarapu@amd.com>
> > > Cc: u-boot@lists.denx.de; j-humphreys@ti.com; Simek, Michal
> > > <michal.simek@amd.com>; jagan@amarulasolutions.com; vigneshr@ti.com;
> > > u- kumar1@ti.com; trini@konsulko.com; seanga2@gmail.com;
> > > caleb.connolly@linaro.org; sjg@chromium.org;
> > > william.zhang@broadcom.com; stefan_b@posteo.net;
> > > quentin.schulz@cherry.de; tudor.ambarus@linaro.org;
> > > Takahiro.Kuwano@infineon.com; git (AMD-Xilinx) <git@amd.com>; Ashok
> > > Reddy Soma <ashok.reddy.soma@amd.com>
> > > Subject: Re: [PATCH] mtd: spi-nor: Enable mt35xu512aba_fixups for
> > > all mt35xx flashes
> > >
> > > On 14:56, Venkatesh Yadav Abbarapu wrote:
> > > Hi Venkatesh,
> > > > Enable mt35xu512aba_fixups for all mt35 series flashes to work in
> > > > DTR mode, and return after nor->fixups is updated, otherwise it
> > > > will get overwritten with macronix_octal_fixups.
> > > > This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU is
> > > > enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.
> > > >
> > > > Additionally, a new flag, "SPI_XFER_SET_DDR", has been introduced
> > > > to instruct the OSPI controller driver to switch to DDR mode.
> > > >
> > > > Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
> > > > Signed-off-by: Venkatesh Yadav Abbarapu
> > > > <venkatesh.abbarapu@amd.com>
> > > > ---
> > > >  drivers/mtd/spi/spi-nor-core.c | 8 +++++++-
> > > >  include/spi.h                  | 1 +
> > > >  2 files changed, 8 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/mtd/spi/spi-nor-core.c
> > > > b/drivers/mtd/spi/spi-nor-core.c index ec841fb13b..8d201433d5
> > > > 100644
> > > > --- a/drivers/mtd/spi/spi-nor-core.c
> > > > +++ b/drivers/mtd/spi/spi-nor-core.c
> > > > @@ -4073,6 +4073,7 @@ static int
> > > > spi_nor_micron_octal_dtr_enable(struct
> > > spi_nor *nor)
> > > >  	if (ret)
> > > >  		return ret;
> > > >
> > > > +	nor->spi->flags |= SPI_XFER_SET_DDR;
> > > >  	buf = SPINOR_MT_OCT_DTR;
> > > >  	op = (struct spi_mem_op)
> > > >
> > > 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
> @@ -4404,8
> > > > +4405,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)  #endif
> > > >
> > > >  #ifdef CONFIG_SPI_FLASH_MT35XU
> > > > -	if (!strcmp(nor->info->name, "mt35xu512aba"))
> > > > +	if (!strcmp(nor->info->name, "mt35xu512aba") ||
> > > > +	    !strcmp(nor->info->name, "mt35xl512aba") ||
> > > > +	    !strcmp(nor->info->name, "mt35xu01g") ||
> > > > +	    !strcmp(nor->info->name, "mt35xu02g")) {
> > > >  		nor->fixups = &mt35xu512aba_fixups;
> > > > +		return;
> > > > +	}
> > > >  #endif
> > > >
> > > >  #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > > > diff --git a/include/spi.h b/include/spi.h index
> > > > 6944773b59..d7fef36662 100644
> > > > --- a/include/spi.h
> > > > +++ b/include/spi.h
> > > > @@ -164,6 +164,7 @@ struct spi_slave {
> > > >  #define SPI_XFER_U_PAGE		BIT(4)
> > > >  #define SPI_XFER_STACKED	BIT(5)
> > > >  #define SPI_XFER_LOWER		BIT(6)
> > > > +#define SPI_XFER_SET_DDR	BIT(7)
> > >
> > > Are we using this anywhere in the Controller driver ? What is the
> > > significance of this flag, when we can send the DDR info through the ops.
> > Yes...we will be checking this
> > If (spi->flags & SPI_XFER_SET_DDR) && op->cmd.dtr) then
> > 	setup the DDR mode in controller driver.
> 
> Is this change going to be for every read/write exec op or in some init function.
> Current driver has this setup dtr mode on checking the opcode.
> Curious to know, what does this extra flag bring something new to the driver.
> 
> Prasanth
I relooked the code and I see this flag is not required anymore. Will update the patch and send next version.

Thanks
Venkatesh
> 
> >
> > I need to send the controller change series.
> >
> > Thanks
> > Venkatesh
> > >
> > > >
> > > >  	/*
> > > >  	 * Flag indicating that the spi-controller has multi chip select
> > > > --
> > > > 2.25.1
> > > >
> > > >
diff mbox series

Patch

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index ec841fb13b..8d201433d5 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -4073,6 +4073,7 @@  static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
 	if (ret)
 		return ret;
 
+	nor->spi->flags |= SPI_XFER_SET_DDR;
 	buf = SPINOR_MT_OCT_DTR;
 	op = (struct spi_mem_op)
 		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
@@ -4404,8 +4405,13 @@  void spi_nor_set_fixups(struct spi_nor *nor)
 #endif
 
 #ifdef CONFIG_SPI_FLASH_MT35XU
-	if (!strcmp(nor->info->name, "mt35xu512aba"))
+	if (!strcmp(nor->info->name, "mt35xu512aba") ||
+	    !strcmp(nor->info->name, "mt35xl512aba") ||
+	    !strcmp(nor->info->name, "mt35xu01g") ||
+	    !strcmp(nor->info->name, "mt35xu02g")) {
 		nor->fixups = &mt35xu512aba_fixups;
+		return;
+	}
 #endif
 
 #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
diff --git a/include/spi.h b/include/spi.h
index 6944773b59..d7fef36662 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -164,6 +164,7 @@  struct spi_slave {
 #define SPI_XFER_U_PAGE		BIT(4)
 #define SPI_XFER_STACKED	BIT(5)
 #define SPI_XFER_LOWER		BIT(6)
+#define SPI_XFER_SET_DDR	BIT(7)
 
 	/*
 	 * Flag indicating that the spi-controller has multi chip select