| Message ID | 20241111020808.38974-4-hal.feng@starfivetech.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Andes |
| Headers | show |
| Series | Support OF_UPSTREAM for StarFive JH7110 | expand |
On 11/11/24 03:07, Hal Feng wrote: > As JH7110 switch to use OF_UPSTREAM dt-bindings, > remove the redundant clock and reset definitions. > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com> After merging patches 1-3 I get: CC env/common.o drivers/clk/starfive/clk-jh7110.c: In function ‘jh7110_stgcrg_init’: drivers/clk/starfive/clk-jh7110.c:498:36: error: ‘JH7110_STGCLK_USB_APB’ undeclared (first use in this function); did you mean ‘JH7110_STGCLK_USB0_APB’? 498 | clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB), | ^~~~~~~~~~~~~~~~~~~~~ We want git bisect to work. This requires successfully building after each individual patch. Best regards Heinrich > --- > .../dt-bindings/clock/starfive,jh7110-crg.h | 258 ------------------ > .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ------------- > 2 files changed, 441 deletions(-) > delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h > delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h > > diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h > deleted file mode 100644 > index b51e3829ff..0000000000 > --- a/include/dt-bindings/clock/starfive,jh7110-crg.h > +++ /dev/null > @@ -1,258 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright (C) 2022 StarFive Technology Co., Ltd. > - * > - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> > - */ > - > -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ > -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ > - > -#define JH7110_SYSCLK_PLL0_OUT 0 > -#define JH7110_SYSCLK_PLL1_OUT 1 > -#define JH7110_SYSCLK_PLL2_OUT 2 > -#define JH7110_PLLCLK_END 3 > - > -#define JH7110_SYSCLK_CPU_ROOT 0 > -#define JH7110_SYSCLK_CPU_CORE 1 > -#define JH7110_SYSCLK_CPU_BUS 2 > -#define JH7110_SYSCLK_GPU_ROOT 3 > -#define JH7110_SYSCLK_PERH_ROOT 4 > -#define JH7110_SYSCLK_BUS_ROOT 5 > -#define JH7110_SYSCLK_NOCSTG_BUS 6 > -#define JH7110_SYSCLK_AXI_CFG0 7 > -#define JH7110_SYSCLK_STG_AXIAHB 8 > -#define JH7110_SYSCLK_AHB0 9 > -#define JH7110_SYSCLK_AHB1 10 > -#define JH7110_SYSCLK_APB_BUS 11 > -#define JH7110_SYSCLK_APB0 12 > -#define JH7110_SYSCLK_PLL0_DIV2 13 > -#define JH7110_SYSCLK_PLL1_DIV2 14 > -#define JH7110_SYSCLK_PLL2_DIV2 15 > -#define JH7110_SYSCLK_AUDIO_ROOT 16 > -#define JH7110_SYSCLK_MCLK_INNER 17 > -#define JH7110_SYSCLK_MCLK 18 > -#define JH7110_SYSCLK_MCLK_OUT 19 > -#define JH7110_SYSCLK_ISP_2X 20 > -#define JH7110_SYSCLK_ISP_AXI 21 > -#define JH7110_SYSCLK_GCLK0 22 > -#define JH7110_SYSCLK_GCLK1 23 > -#define JH7110_SYSCLK_GCLK2 24 > -#define JH7110_SYSCLK_CORE 25 > -#define JH7110_SYSCLK_CORE1 26 > -#define JH7110_SYSCLK_CORE2 27 > -#define JH7110_SYSCLK_CORE3 28 > -#define JH7110_SYSCLK_CORE4 29 > -#define JH7110_SYSCLK_DEBUG 30 > -#define JH7110_SYSCLK_RTC_TOGGLE 31 > -#define JH7110_SYSCLK_TRACE0 32 > -#define JH7110_SYSCLK_TRACE1 33 > -#define JH7110_SYSCLK_TRACE2 34 > -#define JH7110_SYSCLK_TRACE3 35 > -#define JH7110_SYSCLK_TRACE4 36 > -#define JH7110_SYSCLK_TRACE_COM 37 > -#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 > -#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 > -#define JH7110_SYSCLK_OSC_DIV2 40 > -#define JH7110_SYSCLK_PLL1_DIV4 41 > -#define JH7110_SYSCLK_PLL1_DIV8 42 > -#define JH7110_SYSCLK_DDR_BUS 43 > -#define JH7110_SYSCLK_DDR_AXI 44 > -#define JH7110_SYSCLK_GPU_CORE 45 > -#define JH7110_SYSCLK_GPU_CORE_CLK 46 > -#define JH7110_SYSCLK_GPU_SYS_CLK 47 > -#define JH7110_SYSCLK_GPU_APB 48 > -#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 > -#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 > -#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 > -#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 > -#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 > -#define JH7110_SYSCLK_HIFI4_CORE 54 > -#define JH7110_SYSCLK_HIFI4_AXI 55 > -#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 > -#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 > -#define JH7110_SYSCLK_VOUT_SRC 58 > -#define JH7110_SYSCLK_VOUT_AXI 59 > -#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 > -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 > -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 > -#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 > -#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 > -#define JH7110_SYSCLK_JPEGC_AXI 65 > -#define JH7110_SYSCLK_CODAJ12_AXI 66 > -#define JH7110_SYSCLK_CODAJ12_CORE 67 > -#define JH7110_SYSCLK_CODAJ12_APB 68 > -#define JH7110_SYSCLK_VDEC_AXI 69 > -#define JH7110_SYSCLK_WAVE511_AXI 70 > -#define JH7110_SYSCLK_WAVE511_BPU 71 > -#define JH7110_SYSCLK_WAVE511_VCE 72 > -#define JH7110_SYSCLK_WAVE511_APB 73 > -#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 > -#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 > -#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 > -#define JH7110_SYSCLK_VENC_AXI 77 > -#define JH7110_SYSCLK_WAVE420L_AXI 78 > -#define JH7110_SYSCLK_WAVE420L_BPU 79 > -#define JH7110_SYSCLK_WAVE420L_VCE 80 > -#define JH7110_SYSCLK_WAVE420L_APB 81 > -#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 > -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 > -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 > -#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 > -#define JH7110_SYSCLK_AXIMEM2_AXI 86 > -#define JH7110_SYSCLK_QSPI_AHB 87 > -#define JH7110_SYSCLK_QSPI_APB 88 > -#define JH7110_SYSCLK_QSPI_REF_SRC 89 > -#define JH7110_SYSCLK_QSPI_REF 90 > -#define JH7110_SYSCLK_SDIO0_AHB 91 > -#define JH7110_SYSCLK_SDIO1_AHB 92 > -#define JH7110_SYSCLK_SDIO0_SDCARD 93 > -#define JH7110_SYSCLK_SDIO1_SDCARD 94 > -#define JH7110_SYSCLK_USB_125M 95 > -#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 > -#define JH7110_SYSCLK_GMAC1_AHB 97 > -#define JH7110_SYSCLK_GMAC1_AXI 98 > -#define JH7110_SYSCLK_GMAC_SRC 99 > -#define JH7110_SYSCLK_GMAC1_GTXCLK 100 > -#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 > -#define JH7110_SYSCLK_GMAC1_PTP 102 > -#define JH7110_SYSCLK_GMAC1_RX 103 > -#define JH7110_SYSCLK_GMAC1_RX_INV 104 > -#define JH7110_SYSCLK_GMAC1_TX 105 > -#define JH7110_SYSCLK_GMAC1_TX_INV 106 > -#define JH7110_SYSCLK_GMAC1_GTXC 107 > -#define JH7110_SYSCLK_GMAC0_GTXCLK 108 > -#define JH7110_SYSCLK_GMAC0_PTP 109 > -#define JH7110_SYSCLK_GMAC_PHY 110 > -#define JH7110_SYSCLK_GMAC0_GTXC 111 > -#define JH7110_SYSCLK_IOMUX_APB 112 > -#define JH7110_SYSCLK_MAILBOX 113 > -#define JH7110_SYSCLK_INT_CTRL_APB 114 > -#define JH7110_SYSCLK_CAN0_APB 115 > -#define JH7110_SYSCLK_CAN0_TIMER 116 > -#define JH7110_SYSCLK_CAN0_CAN 117 > -#define JH7110_SYSCLK_CAN1_APB 118 > -#define JH7110_SYSCLK_CAN1_TIMER 119 > -#define JH7110_SYSCLK_CAN1_CAN 120 > -#define JH7110_SYSCLK_PWM_APB 121 > -#define JH7110_SYSCLK_WDT_APB 122 > -#define JH7110_SYSCLK_WDT_CORE 123 > -#define JH7110_SYSCLK_TIMER_APB 124 > -#define JH7110_SYSCLK_TIMER0 125 > -#define JH7110_SYSCLK_TIMER1 126 > -#define JH7110_SYSCLK_TIMER2 127 > -#define JH7110_SYSCLK_TIMER3 128 > -#define JH7110_SYSCLK_TEMP_APB 129 > -#define JH7110_SYSCLK_TEMP_CORE 130 > -#define JH7110_SYSCLK_SPI0_APB 131 > -#define JH7110_SYSCLK_SPI1_APB 132 > -#define JH7110_SYSCLK_SPI2_APB 133 > -#define JH7110_SYSCLK_SPI3_APB 134 > -#define JH7110_SYSCLK_SPI4_APB 135 > -#define JH7110_SYSCLK_SPI5_APB 136 > -#define JH7110_SYSCLK_SPI6_APB 137 > -#define JH7110_SYSCLK_I2C0_APB 138 > -#define JH7110_SYSCLK_I2C1_APB 139 > -#define JH7110_SYSCLK_I2C2_APB 140 > -#define JH7110_SYSCLK_I2C3_APB 141 > -#define JH7110_SYSCLK_I2C4_APB 142 > -#define JH7110_SYSCLK_I2C5_APB 143 > -#define JH7110_SYSCLK_I2C6_APB 144 > -#define JH7110_SYSCLK_UART0_APB 145 > -#define JH7110_SYSCLK_UART0_CORE 146 > -#define JH7110_SYSCLK_UART1_APB 147 > -#define JH7110_SYSCLK_UART1_CORE 148 > -#define JH7110_SYSCLK_UART2_APB 149 > -#define JH7110_SYSCLK_UART2_CORE 150 > -#define JH7110_SYSCLK_UART3_APB 151 > -#define JH7110_SYSCLK_UART3_CORE 152 > -#define JH7110_SYSCLK_UART4_APB 153 > -#define JH7110_SYSCLK_UART4_CORE 154 > -#define JH7110_SYSCLK_UART5_APB 155 > -#define JH7110_SYSCLK_UART5_CORE 156 > -#define JH7110_SYSCLK_PWMDAC_APB 157 > -#define JH7110_SYSCLK_PWMDAC_CORE 158 > -#define JH7110_SYSCLK_SPDIF_APB 159 > -#define JH7110_SYSCLK_SPDIF_CORE 160 > -#define JH7110_SYSCLK_I2STX0_APB 161 > -#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 > -#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 > -#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 > -#define JH7110_SYSCLK_I2STX0_BCLK 165 > -#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 > -#define JH7110_SYSCLK_I2STX0_LRCK 167 > -#define JH7110_SYSCLK_I2STX1_APB 168 > -#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 > -#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 > -#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 > -#define JH7110_SYSCLK_I2STX1_BCLK 172 > -#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 > -#define JH7110_SYSCLK_I2STX1_LRCK 174 > -#define JH7110_SYSCLK_I2SRX_APB 175 > -#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 > -#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 > -#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 > -#define JH7110_SYSCLK_I2SRX_BCLK 179 > -#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 > -#define JH7110_SYSCLK_I2SRX_LRCK 181 > -#define JH7110_SYSCLK_PDM_DMIC 182 > -#define JH7110_SYSCLK_PDM_APB 183 > -#define JH7110_SYSCLK_TDM_AHB 184 > -#define JH7110_SYSCLK_TDM_APB 185 > -#define JH7110_SYSCLK_TDM_INTERNAL 186 > -#define JH7110_SYSCLK_TDM_CLK_TDM 187 > -#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 > -#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 > - > -#define JH7110_SYSCLK_END 190 > - > -#define JH7110_AONCLK_OSC_DIV4 0 > -#define JH7110_AONCLK_APB_FUNC 1 > -#define JH7110_AONCLK_GMAC0_AHB 2 > -#define JH7110_AONCLK_GMAC0_AXI 3 > -#define JH7110_AONCLK_GMAC0_RMII_RTX 4 > -#define JH7110_AONCLK_GMAC0_TX 5 > -#define JH7110_AONCLK_GMAC0_TX_INV 6 > -#define JH7110_AONCLK_GMAC0_RX 7 > -#define JH7110_AONCLK_GMAC0_RX_INV 8 > -#define JH7110_AONCLK_OTPC_APB 9 > -#define JH7110_AONCLK_RTC_APB 10 > -#define JH7110_AONCLK_RTC_INTERNAL 11 > -#define JH7110_AONCLK_RTC_32K 12 > -#define JH7110_AONCLK_RTC_CAL 13 > - > -#define JH7110_AONCLK_END 14 > - > -#define JH7110_STGCLK_HIFI4_CORE 0 > -#define JH7110_STGCLK_USB_APB 1 > -#define JH7110_STGCLK_USB_UTMI_APB 2 > -#define JH7110_STGCLK_USB_AXI 3 > -#define JH7110_STGCLK_USB_LPM 4 > -#define JH7110_STGCLK_USB_STB 5 > -#define JH7110_STGCLK_USB_APP_125 6 > -#define JH7110_STGCLK_USB_REFCLK 7 > -#define JH7110_STGCLK_PCIE0_AXI 8 > -#define JH7110_STGCLK_PCIE0_APB 9 > -#define JH7110_STGCLK_PCIE0_TL 10 > -#define JH7110_STGCLK_PCIE1_AXI 11 > -#define JH7110_STGCLK_PCIE1_APB 12 > -#define JH7110_STGCLK_PCIE1_TL 13 > -#define JH7110_STGCLK_PCIE01_MAIN 14 > -#define JH7110_STGCLK_SEC_HCLK 15 > -#define JH7110_STGCLK_SEC_MISCAHB 16 > -#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 > -#define JH7110_STGCLK_MTRX_GRP0_BUS 18 > -#define JH7110_STGCLK_MTRX_GRP0_STG 19 > -#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 > -#define JH7110_STGCLK_MTRX_GRP1_BUS 21 > -#define JH7110_STGCLK_MTRX_GRP1_STG 22 > -#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 > -#define JH7110_STGCLK_E2_RTC 24 > -#define JH7110_STGCLK_E2_CORE 25 > -#define JH7110_STGCLK_E2_DBG 26 > -#define JH7110_STGCLK_DMA1P_AXI 27 > -#define JH7110_STGCLK_DMA1P_AHB 28 > - > -#define JH7110_STGCLK_END 29 > - > -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ > diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h > deleted file mode 100644 > index 1d596581da..0000000000 > --- a/include/dt-bindings/reset/starfive,jh7110-crg.h > +++ /dev/null > @@ -1,183 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright (C) 2022 StarFive Technology Co., Ltd. > - * > - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> > - */ > - > -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ > -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ > - > -/* SYSCRG resets */ > -#define JH7110_SYSRST_JTAG2APB 0 > -#define JH7110_SYSRST_SYSCON 1 > -#define JH7110_SYSRST_IOMUX_APB 2 > -#define JH7110_SYSRST_BUS 3 > -#define JH7110_SYSRST_DEBUG 4 > -#define JH7110_SYSRST_CORE0 5 > -#define JH7110_SYSRST_CORE1 6 > -#define JH7110_SYSRST_CORE2 7 > -#define JH7110_SYSRST_CORE3 8 > -#define JH7110_SYSRST_CORE4 9 > -#define JH7110_SYSRST_CORE0_ST 10 > -#define JH7110_SYSRST_CORE1_ST 11 > -#define JH7110_SYSRST_CORE2_ST 12 > -#define JH7110_SYSRST_CORE3_ST 13 > -#define JH7110_SYSRST_CORE4_ST 14 > -#define JH7110_SYSRST_TRACE0 15 > -#define JH7110_SYSRST_TRACE1 16 > -#define JH7110_SYSRST_TRACE2 17 > -#define JH7110_SYSRST_TRACE3 18 > -#define JH7110_SYSRST_TRACE4 19 > -#define JH7110_SYSRST_TRACE_COM 20 > -#define JH7110_SYSRST_GPU_APB 21 > -#define JH7110_SYSRST_GPU_DOMA 22 > -#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 > -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 > -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 > -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 > -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 > -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 > -#define JH7110_SYSRST_NOC_BUS_DDRC 29 > -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 > -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 > - > -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 > -#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 > -#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 > -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 > -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 > -#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 > -#define JH7110_SYSRST_DDR_AXI 38 > -#define JH7110_SYSRST_DDR_OSC 39 > -#define JH7110_SYSRST_DDR_APB 40 > -#define JH7110_SYSRST_DOM_ISP_TOP_N 41 > -#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 > -#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 > -#define JH7110_SYSRST_CODAJ12_AXI 44 > -#define JH7110_SYSRST_CODAJ12_CORE 45 > -#define JH7110_SYSRST_CODAJ12_APB 46 > -#define JH7110_SYSRST_WAVE511_AXI 47 > -#define JH7110_SYSRST_WAVE511_BPU 48 > -#define JH7110_SYSRST_WAVE511_VCE 49 > -#define JH7110_SYSRST_WAVE511_APB 50 > -#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 > -#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 > -#define JH7110_SYSRST_AXIMEM0_AXI 53 > -#define JH7110_SYSRST_WAVE420L_AXI 54 > -#define JH7110_SYSRST_WAVE420L_BPU 55 > -#define JH7110_SYSRST_WAVE420L_VCE 56 > -#define JH7110_SYSRST_WAVE420L_APB 57 > -#define JH7110_SYSRST_AXIMEM1_AXI 58 > -#define JH7110_SYSRST_AXIMEM2_AXI 59 > -#define JH7110_SYSRST_INTMEM 60 > -#define JH7110_SYSRST_QSPI_AHB 61 > -#define JH7110_SYSRST_QSPI_APB 62 > -#define JH7110_SYSRST_QSPI_REF 63 > - > -#define JH7110_SYSRST_SDIO0_AHB 64 > -#define JH7110_SYSRST_SDIO1_AHB 65 > -#define JH7110_SYSRST_GMAC1_AXI 66 > -#define JH7110_SYSRST_GMAC1_AHB 67 > -#define JH7110_SYSRST_MAILBOX 68 > -#define JH7110_SYSRST_SPI0_APB 69 > -#define JH7110_SYSRST_SPI1_APB 70 > -#define JH7110_SYSRST_SPI2_APB 71 > -#define JH7110_SYSRST_SPI3_APB 72 > -#define JH7110_SYSRST_SPI4_APB 73 > -#define JH7110_SYSRST_SPI5_APB 74 > -#define JH7110_SYSRST_SPI6_APB 75 > -#define JH7110_SYSRST_I2C0_APB 76 > -#define JH7110_SYSRST_I2C1_APB 77 > -#define JH7110_SYSRST_I2C2_APB 78 > -#define JH7110_SYSRST_I2C3_APB 79 > -#define JH7110_SYSRST_I2C4_APB 80 > -#define JH7110_SYSRST_I2C5_APB 81 > -#define JH7110_SYSRST_I2C6_APB 82 > -#define JH7110_SYSRST_UART0_APB 83 > -#define JH7110_SYSRST_UART0_CORE 84 > -#define JH7110_SYSRST_UART1_APB 85 > -#define JH7110_SYSRST_UART1_CORE 86 > -#define JH7110_SYSRST_UART2_APB 87 > -#define JH7110_SYSRST_UART2_CORE 88 > -#define JH7110_SYSRST_UART3_APB 89 > -#define JH7110_SYSRST_UART3_CORE 90 > -#define JH7110_SYSRST_UART4_APB 91 > -#define JH7110_SYSRST_UART4_CORE 92 > -#define JH7110_SYSRST_UART5_APB 93 > -#define JH7110_SYSRST_UART5_CORE 94 > -#define JH7110_SYSRST_SPDIF_APB 95 > - > -#define JH7110_SYSRST_PWMDAC_APB 96 > -#define JH7110_SYSRST_PDM_DMIC 97 > -#define JH7110_SYSRST_PDM_APB 98 > -#define JH7110_SYSRST_I2SRX_APB 99 > -#define JH7110_SYSRST_I2SRX_BCLK 100 > -#define JH7110_SYSRST_I2STX0_APB 101 > -#define JH7110_SYSRST_I2STX0_BCLK 102 > -#define JH7110_SYSRST_I2STX1_APB 103 > -#define JH7110_SYSRST_I2STX1_BCLK 104 > -#define JH7110_SYSRST_TDM_AHB 105 > -#define JH7110_SYSRST_TDM_CORE 106 > -#define JH7110_SYSRST_TDM_APB 107 > -#define JH7110_SYSRST_PWM_APB 108 > -#define JH7110_SYSRST_WDT_APB 109 > -#define JH7110_SYSRST_WDT_CORE 110 > -#define JH7110_SYSRST_CAN0_APB 111 > -#define JH7110_SYSRST_CAN0_CORE 112 > -#define JH7110_SYSRST_CAN0_TIMER 113 > -#define JH7110_SYSRST_CAN1_APB 114 > -#define JH7110_SYSRST_CAN1_CORE 115 > -#define JH7110_SYSRST_CAN1_TIMER 116 > -#define JH7110_SYSRST_TIMER_APB 117 > -#define JH7110_SYSRST_TIMER0 118 > -#define JH7110_SYSRST_TIMER1 119 > -#define JH7110_SYSRST_TIMER2 120 > -#define JH7110_SYSRST_TIMER3 121 > -#define JH7110_SYSRST_INT_CTRL_APB 122 > -#define JH7110_SYSRST_TEMP_APB 123 > -#define JH7110_SYSRST_TEMP_CORE 124 > -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 > - > -#define JH7110_SYSRST_END 126 > - > -/* AONCRG resets */ > -#define JH7110_AONRST_GMAC0_AXI 0 > -#define JH7110_AONRST_GMAC0_AHB 1 > -#define JH7110_AONRST_IOMUX 2 > -#define JH7110_AONRST_PMU_APB 3 > -#define JH7110_AONRST_PMU_WKUP 4 > -#define JH7110_AONRST_RTC_APB 5 > -#define JH7110_AONRST_RTC_CAL 6 > -#define JH7110_AONRST_RTC_32K 7 > - > -#define JH7110_AONRST_END 8 > - > -/* STGCRG resets */ > -#define JH7110_STGRST_SYSCON_PRESETN 0 > -#define JH7110_STGRST_HIFI4_CORE 1 > -#define JH7110_STGRST_HIFI4_AXI 2 > -#define JH7110_STGRST_SEC_TOP_HRESETN 3 > -#define JH7110_STGRST_E24_CORE 4 > -#define JH7110_STGRST_DMA1P_AXI 5 > -#define JH7110_STGRST_DMA1P_AHB 6 > -#define JH7110_STGRST_USB_AXI 7 > -#define JH7110_STGRST_USB_APB 8 > -#define JH7110_STGRST_USB_UTMI_APB 9 > -#define JH7110_STGRST_USB_PWRUP 10 > -#define JH7110_STGRST_PCIE0_MST0 11 > -#define JH7110_STGRST_PCIE0_SLV0 12 > -#define JH7110_STGRST_PCIE0_SLV 13 > -#define JH7110_STGRST_PCIE0_BRG 14 > -#define JH7110_STGRST_PCIE0_CORE 15 > -#define JH7110_STGRST_PCIE0_APB 16 > -#define JH7110_STGRST_PCIE1_MST0 17 > -#define JH7110_STGRST_PCIE1_SLV0 18 > -#define JH7110_STGRST_PCIE1_SLV 19 > -#define JH7110_STGRST_PCIE1_BRG 20 > -#define JH7110_STGRST_PCIE1_CORE 21 > -#define JH7110_STGRST_PCIE1_APB 22 > - > -#define JH7110_STGRST_END 23 > - > -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
On 11/11/2024 6:52 PM, Heinrich Schuchardt wrote: > On 11/11/24 03:07, Hal Feng wrote: >> As JH7110 switch to use OF_UPSTREAM dt-bindings, >> remove the redundant clock and reset definitions. >> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> > > After merging patches 1-3 I get: > > CC env/common.o > drivers/clk/starfive/clk-jh7110.c: In function ‘jh7110_stgcrg_init’: > drivers/clk/starfive/clk-jh7110.c:498:36: error: ‘JH7110_STGCLK_USB_APB’ > undeclared (first use in this function); did you mean > ‘JH7110_STGCLK_USB0_APB’? > 498 | clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB), > | ^~~~~~~~~~~~~~~~~~~~~ > > We want git bisect to work. This requires successfully building after > each individual patch. > Got it. Will make some changes to make sure git bisect works. Thanks. Best regards, Hal
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h deleted file mode 100644 index b51e3829ff..0000000000 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> - */ - -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ - -#define JH7110_SYSCLK_PLL0_OUT 0 -#define JH7110_SYSCLK_PLL1_OUT 1 -#define JH7110_SYSCLK_PLL2_OUT 2 -#define JH7110_PLLCLK_END 3 - -#define JH7110_SYSCLK_CPU_ROOT 0 -#define JH7110_SYSCLK_CPU_CORE 1 -#define JH7110_SYSCLK_CPU_BUS 2 -#define JH7110_SYSCLK_GPU_ROOT 3 -#define JH7110_SYSCLK_PERH_ROOT 4 -#define JH7110_SYSCLK_BUS_ROOT 5 -#define JH7110_SYSCLK_NOCSTG_BUS 6 -#define JH7110_SYSCLK_AXI_CFG0 7 -#define JH7110_SYSCLK_STG_AXIAHB 8 -#define JH7110_SYSCLK_AHB0 9 -#define JH7110_SYSCLK_AHB1 10 -#define JH7110_SYSCLK_APB_BUS 11 -#define JH7110_SYSCLK_APB0 12 -#define JH7110_SYSCLK_PLL0_DIV2 13 -#define JH7110_SYSCLK_PLL1_DIV2 14 -#define JH7110_SYSCLK_PLL2_DIV2 15 -#define JH7110_SYSCLK_AUDIO_ROOT 16 -#define JH7110_SYSCLK_MCLK_INNER 17 -#define JH7110_SYSCLK_MCLK 18 -#define JH7110_SYSCLK_MCLK_OUT 19 -#define JH7110_SYSCLK_ISP_2X 20 -#define JH7110_SYSCLK_ISP_AXI 21 -#define JH7110_SYSCLK_GCLK0 22 -#define JH7110_SYSCLK_GCLK1 23 -#define JH7110_SYSCLK_GCLK2 24 -#define JH7110_SYSCLK_CORE 25 -#define JH7110_SYSCLK_CORE1 26 -#define JH7110_SYSCLK_CORE2 27 -#define JH7110_SYSCLK_CORE3 28 -#define JH7110_SYSCLK_CORE4 29 -#define JH7110_SYSCLK_DEBUG 30 -#define JH7110_SYSCLK_RTC_TOGGLE 31 -#define JH7110_SYSCLK_TRACE0 32 -#define JH7110_SYSCLK_TRACE1 33 -#define JH7110_SYSCLK_TRACE2 34 -#define JH7110_SYSCLK_TRACE3 35 -#define JH7110_SYSCLK_TRACE4 36 -#define JH7110_SYSCLK_TRACE_COM 37 -#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 -#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 -#define JH7110_SYSCLK_OSC_DIV2 40 -#define JH7110_SYSCLK_PLL1_DIV4 41 -#define JH7110_SYSCLK_PLL1_DIV8 42 -#define JH7110_SYSCLK_DDR_BUS 43 -#define JH7110_SYSCLK_DDR_AXI 44 -#define JH7110_SYSCLK_GPU_CORE 45 -#define JH7110_SYSCLK_GPU_CORE_CLK 46 -#define JH7110_SYSCLK_GPU_SYS_CLK 47 -#define JH7110_SYSCLK_GPU_APB 48 -#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 -#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 -#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 -#define JH7110_SYSCLK_HIFI4_CORE 54 -#define JH7110_SYSCLK_HIFI4_AXI 55 -#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 -#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 -#define JH7110_SYSCLK_VOUT_SRC 58 -#define JH7110_SYSCLK_VOUT_AXI 59 -#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 -#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 -#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 -#define JH7110_SYSCLK_JPEGC_AXI 65 -#define JH7110_SYSCLK_CODAJ12_AXI 66 -#define JH7110_SYSCLK_CODAJ12_CORE 67 -#define JH7110_SYSCLK_CODAJ12_APB 68 -#define JH7110_SYSCLK_VDEC_AXI 69 -#define JH7110_SYSCLK_WAVE511_AXI 70 -#define JH7110_SYSCLK_WAVE511_BPU 71 -#define JH7110_SYSCLK_WAVE511_VCE 72 -#define JH7110_SYSCLK_WAVE511_APB 73 -#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 -#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 -#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 -#define JH7110_SYSCLK_VENC_AXI 77 -#define JH7110_SYSCLK_WAVE420L_AXI 78 -#define JH7110_SYSCLK_WAVE420L_BPU 79 -#define JH7110_SYSCLK_WAVE420L_VCE 80 -#define JH7110_SYSCLK_WAVE420L_APB 81 -#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 -#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 -#define JH7110_SYSCLK_AXIMEM2_AXI 86 -#define JH7110_SYSCLK_QSPI_AHB 87 -#define JH7110_SYSCLK_QSPI_APB 88 -#define JH7110_SYSCLK_QSPI_REF_SRC 89 -#define JH7110_SYSCLK_QSPI_REF 90 -#define JH7110_SYSCLK_SDIO0_AHB 91 -#define JH7110_SYSCLK_SDIO1_AHB 92 -#define JH7110_SYSCLK_SDIO0_SDCARD 93 -#define JH7110_SYSCLK_SDIO1_SDCARD 94 -#define JH7110_SYSCLK_USB_125M 95 -#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 -#define JH7110_SYSCLK_GMAC1_AHB 97 -#define JH7110_SYSCLK_GMAC1_AXI 98 -#define JH7110_SYSCLK_GMAC_SRC 99 -#define JH7110_SYSCLK_GMAC1_GTXCLK 100 -#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 -#define JH7110_SYSCLK_GMAC1_PTP 102 -#define JH7110_SYSCLK_GMAC1_RX 103 -#define JH7110_SYSCLK_GMAC1_RX_INV 104 -#define JH7110_SYSCLK_GMAC1_TX 105 -#define JH7110_SYSCLK_GMAC1_TX_INV 106 -#define JH7110_SYSCLK_GMAC1_GTXC 107 -#define JH7110_SYSCLK_GMAC0_GTXCLK 108 -#define JH7110_SYSCLK_GMAC0_PTP 109 -#define JH7110_SYSCLK_GMAC_PHY 110 -#define JH7110_SYSCLK_GMAC0_GTXC 111 -#define JH7110_SYSCLK_IOMUX_APB 112 -#define JH7110_SYSCLK_MAILBOX 113 -#define JH7110_SYSCLK_INT_CTRL_APB 114 -#define JH7110_SYSCLK_CAN0_APB 115 -#define JH7110_SYSCLK_CAN0_TIMER 116 -#define JH7110_SYSCLK_CAN0_CAN 117 -#define JH7110_SYSCLK_CAN1_APB 118 -#define JH7110_SYSCLK_CAN1_TIMER 119 -#define JH7110_SYSCLK_CAN1_CAN 120 -#define JH7110_SYSCLK_PWM_APB 121 -#define JH7110_SYSCLK_WDT_APB 122 -#define JH7110_SYSCLK_WDT_CORE 123 -#define JH7110_SYSCLK_TIMER_APB 124 -#define JH7110_SYSCLK_TIMER0 125 -#define JH7110_SYSCLK_TIMER1 126 -#define JH7110_SYSCLK_TIMER2 127 -#define JH7110_SYSCLK_TIMER3 128 -#define JH7110_SYSCLK_TEMP_APB 129 -#define JH7110_SYSCLK_TEMP_CORE 130 -#define JH7110_SYSCLK_SPI0_APB 131 -#define JH7110_SYSCLK_SPI1_APB 132 -#define JH7110_SYSCLK_SPI2_APB 133 -#define JH7110_SYSCLK_SPI3_APB 134 -#define JH7110_SYSCLK_SPI4_APB 135 -#define JH7110_SYSCLK_SPI5_APB 136 -#define JH7110_SYSCLK_SPI6_APB 137 -#define JH7110_SYSCLK_I2C0_APB 138 -#define JH7110_SYSCLK_I2C1_APB 139 -#define JH7110_SYSCLK_I2C2_APB 140 -#define JH7110_SYSCLK_I2C3_APB 141 -#define JH7110_SYSCLK_I2C4_APB 142 -#define JH7110_SYSCLK_I2C5_APB 143 -#define JH7110_SYSCLK_I2C6_APB 144 -#define JH7110_SYSCLK_UART0_APB 145 -#define JH7110_SYSCLK_UART0_CORE 146 -#define JH7110_SYSCLK_UART1_APB 147 -#define JH7110_SYSCLK_UART1_CORE 148 -#define JH7110_SYSCLK_UART2_APB 149 -#define JH7110_SYSCLK_UART2_CORE 150 -#define JH7110_SYSCLK_UART3_APB 151 -#define JH7110_SYSCLK_UART3_CORE 152 -#define JH7110_SYSCLK_UART4_APB 153 -#define JH7110_SYSCLK_UART4_CORE 154 -#define JH7110_SYSCLK_UART5_APB 155 -#define JH7110_SYSCLK_UART5_CORE 156 -#define JH7110_SYSCLK_PWMDAC_APB 157 -#define JH7110_SYSCLK_PWMDAC_CORE 158 -#define JH7110_SYSCLK_SPDIF_APB 159 -#define JH7110_SYSCLK_SPDIF_CORE 160 -#define JH7110_SYSCLK_I2STX0_APB 161 -#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 -#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 -#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 -#define JH7110_SYSCLK_I2STX0_BCLK 165 -#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 -#define JH7110_SYSCLK_I2STX0_LRCK 167 -#define JH7110_SYSCLK_I2STX1_APB 168 -#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 -#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 -#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 -#define JH7110_SYSCLK_I2STX1_BCLK 172 -#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 -#define JH7110_SYSCLK_I2STX1_LRCK 174 -#define JH7110_SYSCLK_I2SRX_APB 175 -#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 -#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 -#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 -#define JH7110_SYSCLK_I2SRX_BCLK 179 -#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 -#define JH7110_SYSCLK_I2SRX_LRCK 181 -#define JH7110_SYSCLK_PDM_DMIC 182 -#define JH7110_SYSCLK_PDM_APB 183 -#define JH7110_SYSCLK_TDM_AHB 184 -#define JH7110_SYSCLK_TDM_APB 185 -#define JH7110_SYSCLK_TDM_INTERNAL 186 -#define JH7110_SYSCLK_TDM_CLK_TDM 187 -#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 -#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 - -#define JH7110_SYSCLK_END 190 - -#define JH7110_AONCLK_OSC_DIV4 0 -#define JH7110_AONCLK_APB_FUNC 1 -#define JH7110_AONCLK_GMAC0_AHB 2 -#define JH7110_AONCLK_GMAC0_AXI 3 -#define JH7110_AONCLK_GMAC0_RMII_RTX 4 -#define JH7110_AONCLK_GMAC0_TX 5 -#define JH7110_AONCLK_GMAC0_TX_INV 6 -#define JH7110_AONCLK_GMAC0_RX 7 -#define JH7110_AONCLK_GMAC0_RX_INV 8 -#define JH7110_AONCLK_OTPC_APB 9 -#define JH7110_AONCLK_RTC_APB 10 -#define JH7110_AONCLK_RTC_INTERNAL 11 -#define JH7110_AONCLK_RTC_32K 12 -#define JH7110_AONCLK_RTC_CAL 13 - -#define JH7110_AONCLK_END 14 - -#define JH7110_STGCLK_HIFI4_CORE 0 -#define JH7110_STGCLK_USB_APB 1 -#define JH7110_STGCLK_USB_UTMI_APB 2 -#define JH7110_STGCLK_USB_AXI 3 -#define JH7110_STGCLK_USB_LPM 4 -#define JH7110_STGCLK_USB_STB 5 -#define JH7110_STGCLK_USB_APP_125 6 -#define JH7110_STGCLK_USB_REFCLK 7 -#define JH7110_STGCLK_PCIE0_AXI 8 -#define JH7110_STGCLK_PCIE0_APB 9 -#define JH7110_STGCLK_PCIE0_TL 10 -#define JH7110_STGCLK_PCIE1_AXI 11 -#define JH7110_STGCLK_PCIE1_APB 12 -#define JH7110_STGCLK_PCIE1_TL 13 -#define JH7110_STGCLK_PCIE01_MAIN 14 -#define JH7110_STGCLK_SEC_HCLK 15 -#define JH7110_STGCLK_SEC_MISCAHB 16 -#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 -#define JH7110_STGCLK_MTRX_GRP0_BUS 18 -#define JH7110_STGCLK_MTRX_GRP0_STG 19 -#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 -#define JH7110_STGCLK_MTRX_GRP1_BUS 21 -#define JH7110_STGCLK_MTRX_GRP1_STG 22 -#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 -#define JH7110_STGCLK_E2_RTC 24 -#define JH7110_STGCLK_E2_CORE 25 -#define JH7110_STGCLK_E2_DBG 26 -#define JH7110_STGCLK_DMA1P_AXI 27 -#define JH7110_STGCLK_DMA1P_AHB 28 - -#define JH7110_STGCLK_END 29 - -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h deleted file mode 100644 index 1d596581da..0000000000 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang <yanhong.wang@starfivetech.com> - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ - -/* SYSCRG resets */ -#define JH7110_SYSRST_JTAG2APB 0 -#define JH7110_SYSRST_SYSCON 1 -#define JH7110_SYSRST_IOMUX_APB 2 -#define JH7110_SYSRST_BUS 3 -#define JH7110_SYSRST_DEBUG 4 -#define JH7110_SYSRST_CORE0 5 -#define JH7110_SYSRST_CORE1 6 -#define JH7110_SYSRST_CORE2 7 -#define JH7110_SYSRST_CORE3 8 -#define JH7110_SYSRST_CORE4 9 -#define JH7110_SYSRST_CORE0_ST 10 -#define JH7110_SYSRST_CORE1_ST 11 -#define JH7110_SYSRST_CORE2_ST 12 -#define JH7110_SYSRST_CORE3_ST 13 -#define JH7110_SYSRST_CORE4_ST 14 -#define JH7110_SYSRST_TRACE0 15 -#define JH7110_SYSRST_TRACE1 16 -#define JH7110_SYSRST_TRACE2 17 -#define JH7110_SYSRST_TRACE3 18 -#define JH7110_SYSRST_TRACE4 19 -#define JH7110_SYSRST_TRACE_COM 20 -#define JH7110_SYSRST_GPU_APB 21 -#define JH7110_SYSRST_GPU_DOMA 22 -#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 -#define JH7110_SYSRST_NOC_BUS_DDRC 29 -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 - -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 -#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 -#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 -#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 -#define JH7110_SYSRST_DDR_AXI 38 -#define JH7110_SYSRST_DDR_OSC 39 -#define JH7110_SYSRST_DDR_APB 40 -#define JH7110_SYSRST_DOM_ISP_TOP_N 41 -#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 -#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 -#define JH7110_SYSRST_CODAJ12_AXI 44 -#define JH7110_SYSRST_CODAJ12_CORE 45 -#define JH7110_SYSRST_CODAJ12_APB 46 -#define JH7110_SYSRST_WAVE511_AXI 47 -#define JH7110_SYSRST_WAVE511_BPU 48 -#define JH7110_SYSRST_WAVE511_VCE 49 -#define JH7110_SYSRST_WAVE511_APB 50 -#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 -#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 -#define JH7110_SYSRST_AXIMEM0_AXI 53 -#define JH7110_SYSRST_WAVE420L_AXI 54 -#define JH7110_SYSRST_WAVE420L_BPU 55 -#define JH7110_SYSRST_WAVE420L_VCE 56 -#define JH7110_SYSRST_WAVE420L_APB 57 -#define JH7110_SYSRST_AXIMEM1_AXI 58 -#define JH7110_SYSRST_AXIMEM2_AXI 59 -#define JH7110_SYSRST_INTMEM 60 -#define JH7110_SYSRST_QSPI_AHB 61 -#define JH7110_SYSRST_QSPI_APB 62 -#define JH7110_SYSRST_QSPI_REF 63 - -#define JH7110_SYSRST_SDIO0_AHB 64 -#define JH7110_SYSRST_SDIO1_AHB 65 -#define JH7110_SYSRST_GMAC1_AXI 66 -#define JH7110_SYSRST_GMAC1_AHB 67 -#define JH7110_SYSRST_MAILBOX 68 -#define JH7110_SYSRST_SPI0_APB 69 -#define JH7110_SYSRST_SPI1_APB 70 -#define JH7110_SYSRST_SPI2_APB 71 -#define JH7110_SYSRST_SPI3_APB 72 -#define JH7110_SYSRST_SPI4_APB 73 -#define JH7110_SYSRST_SPI5_APB 74 -#define JH7110_SYSRST_SPI6_APB 75 -#define JH7110_SYSRST_I2C0_APB 76 -#define JH7110_SYSRST_I2C1_APB 77 -#define JH7110_SYSRST_I2C2_APB 78 -#define JH7110_SYSRST_I2C3_APB 79 -#define JH7110_SYSRST_I2C4_APB 80 -#define JH7110_SYSRST_I2C5_APB 81 -#define JH7110_SYSRST_I2C6_APB 82 -#define JH7110_SYSRST_UART0_APB 83 -#define JH7110_SYSRST_UART0_CORE 84 -#define JH7110_SYSRST_UART1_APB 85 -#define JH7110_SYSRST_UART1_CORE 86 -#define JH7110_SYSRST_UART2_APB 87 -#define JH7110_SYSRST_UART2_CORE 88 -#define JH7110_SYSRST_UART3_APB 89 -#define JH7110_SYSRST_UART3_CORE 90 -#define JH7110_SYSRST_UART4_APB 91 -#define JH7110_SYSRST_UART4_CORE 92 -#define JH7110_SYSRST_UART5_APB 93 -#define JH7110_SYSRST_UART5_CORE 94 -#define JH7110_SYSRST_SPDIF_APB 95 - -#define JH7110_SYSRST_PWMDAC_APB 96 -#define JH7110_SYSRST_PDM_DMIC 97 -#define JH7110_SYSRST_PDM_APB 98 -#define JH7110_SYSRST_I2SRX_APB 99 -#define JH7110_SYSRST_I2SRX_BCLK 100 -#define JH7110_SYSRST_I2STX0_APB 101 -#define JH7110_SYSRST_I2STX0_BCLK 102 -#define JH7110_SYSRST_I2STX1_APB 103 -#define JH7110_SYSRST_I2STX1_BCLK 104 -#define JH7110_SYSRST_TDM_AHB 105 -#define JH7110_SYSRST_TDM_CORE 106 -#define JH7110_SYSRST_TDM_APB 107 -#define JH7110_SYSRST_PWM_APB 108 -#define JH7110_SYSRST_WDT_APB 109 -#define JH7110_SYSRST_WDT_CORE 110 -#define JH7110_SYSRST_CAN0_APB 111 -#define JH7110_SYSRST_CAN0_CORE 112 -#define JH7110_SYSRST_CAN0_TIMER 113 -#define JH7110_SYSRST_CAN1_APB 114 -#define JH7110_SYSRST_CAN1_CORE 115 -#define JH7110_SYSRST_CAN1_TIMER 116 -#define JH7110_SYSRST_TIMER_APB 117 -#define JH7110_SYSRST_TIMER0 118 -#define JH7110_SYSRST_TIMER1 119 -#define JH7110_SYSRST_TIMER2 120 -#define JH7110_SYSRST_TIMER3 121 -#define JH7110_SYSRST_INT_CTRL_APB 122 -#define JH7110_SYSRST_TEMP_APB 123 -#define JH7110_SYSRST_TEMP_CORE 124 -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 - -#define JH7110_SYSRST_END 126 - -/* AONCRG resets */ -#define JH7110_AONRST_GMAC0_AXI 0 -#define JH7110_AONRST_GMAC0_AHB 1 -#define JH7110_AONRST_IOMUX 2 -#define JH7110_AONRST_PMU_APB 3 -#define JH7110_AONRST_PMU_WKUP 4 -#define JH7110_AONRST_RTC_APB 5 -#define JH7110_AONRST_RTC_CAL 6 -#define JH7110_AONRST_RTC_32K 7 - -#define JH7110_AONRST_END 8 - -/* STGCRG resets */ -#define JH7110_STGRST_SYSCON_PRESETN 0 -#define JH7110_STGRST_HIFI4_CORE 1 -#define JH7110_STGRST_HIFI4_AXI 2 -#define JH7110_STGRST_SEC_TOP_HRESETN 3 -#define JH7110_STGRST_E24_CORE 4 -#define JH7110_STGRST_DMA1P_AXI 5 -#define JH7110_STGRST_DMA1P_AHB 6 -#define JH7110_STGRST_USB_AXI 7 -#define JH7110_STGRST_USB_APB 8 -#define JH7110_STGRST_USB_UTMI_APB 9 -#define JH7110_STGRST_USB_PWRUP 10 -#define JH7110_STGRST_PCIE0_MST0 11 -#define JH7110_STGRST_PCIE0_SLV0 12 -#define JH7110_STGRST_PCIE0_SLV 13 -#define JH7110_STGRST_PCIE0_BRG 14 -#define JH7110_STGRST_PCIE0_CORE 15 -#define JH7110_STGRST_PCIE0_APB 16 -#define JH7110_STGRST_PCIE1_MST0 17 -#define JH7110_STGRST_PCIE1_SLV0 18 -#define JH7110_STGRST_PCIE1_SLV 19 -#define JH7110_STGRST_PCIE1_BRG 20 -#define JH7110_STGRST_PCIE1_CORE 21 -#define JH7110_STGRST_PCIE1_APB 22 - -#define JH7110_STGRST_END 23 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
As JH7110 switch to use OF_UPSTREAM dt-bindings, remove the redundant clock and reset definitions. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> --- .../dt-bindings/clock/starfive,jh7110-crg.h | 258 ------------------ .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ------------- 2 files changed, 441 deletions(-) delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h