| Message ID | 20241002-sm8150-qmp-phy-v1-1-719695ad2f1e@devpi.de |
|---|---|
| State | New |
| Delegated to: | Caleb Connolly |
| Headers | show |
| Series | phy: qcom: Add SM8150 to QMP UFS PHY driver | expand |
On 02/10/2024 20:52, Julius Lehmann wrote: > Copy PHY tables over from Linux to support SM8150 > > --- > As the title suggests, this is really just a simple patch to add Qualcomm's SM8150 SoC to the QMP UFS PHY driver. It has been tested to work with https://lore.kernel.org/u-boot/20240930-topic-ufs-enhancements-v3-0-58234f84ab89@linaro.org/ on a Xiaomi Mi Pad 5. > > Signed-off-by: Julius Lehmann <lehmanju@devpi.de> > --- > drivers/phy/qcom/phy-qcom-qmp-ufs.c | 62 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c > index 8908a34df548340556d92ac8ca488dbbbd0e293a..11f92b8261aff48dddb63cd8de31db3716a45fb4 100644 > --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c > @@ -189,6 +189,29 @@ static const struct qmp_ufs_init_tbl sdm845_ufsphy_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > }; > > +static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_tx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), > +}; > + > +static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), > + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), > +}; > + > static const struct qmp_ufs_init_tbl sm8150_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), > QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), > @@ -623,6 +646,44 @@ static const struct qmp_ufs_cfg sdm845_ufsphy_cfg = { > .no_pcs_sw_reset = true, > }; > > +static const struct qmp_ufs_cfg sm8150_ufsphy_cfg = { > + .lanes = 2, > + > + .offsets = &qmp_ufs_offsets, > + > + .tbls = { > + .serdes = sm8150_ufsphy_serdes, > + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), > + .tx = sm8150_ufsphy_tx, > + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), > + .rx = sm8150_ufsphy_rx, > + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), > + .pcs = sm8150_ufsphy_pcs, > + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), > + }, > + .tbls_hs_b = { > + .serdes = sm8150_ufsphy_hs_b_serdes, > + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), > + }, > + .tbls_hs_g4 = { > + .tx = sm8150_ufsphy_hs_g4_tx, > + .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), > + .rx = sm8150_ufsphy_hs_g4_rx, > + .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), > + .pcs = sm8150_ufsphy_hs_g4_pcs, > + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), > + }, > + .clk_list = sdm845_ufs_phy_clk_l, > + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), > + .vreg_list = qmp_ufs_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), > + .reset_list = qmp_ufs_reset_l, > + .num_resets = ARRAY_SIZE(qmp_ufs_reset_l), > + .regs = ufsphy_v4_regs_layout, > + > + .no_pcs_sw_reset = false, > +}; > + > static const struct qmp_ufs_cfg sm8250_ufsphy_cfg = { > .lanes = 2, > > @@ -1100,6 +1161,7 @@ static struct phy_ops qmp_ufs_ops = { > > static const struct udevice_id qmp_ufs_ids[] = { > { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, > + { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, > { .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg }, > { .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg }, > { .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg }, > > --- > base-commit: 2d21dd440e052bb2c8ccc9fa3137ab40c8f87f14 > change-id: 20241002-sm8150-qmp-phy-ddb990d1a1bc > > Best regards, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 8908a34df548340556d92ac8ca488dbbbd0e293a..11f92b8261aff48dddb63cd8de31db3716a45fb4 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -189,6 +189,29 @@ static const struct qmp_ufs_init_tbl sdm845_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + +static const struct qmp_ufs_init_tbl sm8150_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_ufs_init_tbl sm8150_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), @@ -623,6 +646,44 @@ static const struct qmp_ufs_cfg sdm845_ufsphy_cfg = { .no_pcs_sw_reset = true, }; +static const struct qmp_ufs_cfg sm8150_ufsphy_cfg = { + .lanes = 2, + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8150_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx = sm8150_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), + .rx = sm8150_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs = sm8150_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8150_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8150_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx = sm8150_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs = sm8150_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_ufs_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), + .reset_list = qmp_ufs_reset_l, + .num_resets = ARRAY_SIZE(qmp_ufs_reset_l), + .regs = ufsphy_v4_regs_layout, + + .no_pcs_sw_reset = false, +}; + static const struct qmp_ufs_cfg sm8250_ufsphy_cfg = { .lanes = 2, @@ -1100,6 +1161,7 @@ static struct phy_ops qmp_ufs_ops = { static const struct udevice_id qmp_ufs_ids[] = { { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, + { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, { .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg }, { .compatible = "qcom,sm8550-qmp-ufs-phy", .data = (ulong)&sm8550_ufsphy_cfg }, { .compatible = "qcom,sm8650-qmp-ufs-phy", .data = (ulong)&sm8650_ufsphy_cfg },
Copy PHY tables over from Linux to support SM8150 --- As the title suggests, this is really just a simple patch to add Qualcomm's SM8150 SoC to the QMP UFS PHY driver. It has been tested to work with https://lore.kernel.org/u-boot/20240930-topic-ufs-enhancements-v3-0-58234f84ab89@linaro.org/ on a Xiaomi Mi Pad 5. Signed-off-by: Julius Lehmann <lehmanju@devpi.de> --- drivers/phy/qcom/phy-qcom-qmp-ufs.c | 62 +++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) --- base-commit: 2d21dd440e052bb2c8ccc9fa3137ab40c8f87f14 change-id: 20241002-sm8150-qmp-phy-ddb990d1a1bc Best regards,