| Message ID | 20240926183111.1324284-1-paulk@sys-base.io |
|---|---|
| State | New |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | [1/4] rockchip: rk3399-roc-pc: Hook sysreset gpio to enable full reset | expand |
Hi Paul, I'm not entirely sure on whose side the issue is, but I didn't receive your mails, either from the U-Boot mailing list or directly from the Cc field. I however could find the patch on lore.kernel.org... and I also received yours and Dragan's exchange on patch 4 (but not the patch itself). Any chance you received something from my mail server? Does anyone in Cc of this mail actually received the mail? On 9/26/24 8:31 PM, Paul Kocialkowski wrote: > From: Paul Kocialkowski <contact@paulk.fr> > > The reset mechanism used by Linux to reset the SoC is known to only > partially reset the logic. A mechanism is implemented in > rk3399_force_power_on_reset to use a GPIO connected to the PMIC's > over-temperature (OTP) reset pin, which fully resets all logic. > > Hook the associated GPIO where the function expects it to enable this > reset mechanism and avoid any possible side-effect of partially-reset > units. > > Without this patch, reading from the micro sd slot fails after a reset. > With this mechanism, U-Boot is able to boot from it reliably. > > Signed-off-by: Paul Kocialkowski <contact@paulk.fr> > --- > arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > index aecf7dbe383c..883d399a06a3 100644 > --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > @@ -7,6 +7,10 @@ > #include "rk3399-sdram-lpddr4-100.dtsi" > > / { > + config { > + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; I think this is the wrong pin to use. The routing of GPIO1_A6 is similar on RK3399 Puma and Pine64 RockPro64, but it differs massively for the Firefly Roc PC. However, a similar routing is done for GPIO1_A5 on the Firefly, I believe that one is more appropriate. What do you think? Cheers, Quentin
Hi Quentin, Thanks for looking into this! Le Fri 27 Sep 24, 11:25, Quentin Schulz a écrit : > I'm not entirely sure on whose side the issue is, but I didn't receive your > mails, either from the U-Boot mailing list or directly from the Cc field. I > however could find the patch on lore.kernel.org... and I also received yours > and Dragan's exchange on patch 4 (but not the patch itself). Any chance you > received something from my mail server? Does anyone in Cc of this mail > actually received the mail? No automatic reply from your mail server and the logs look good on my side, with a 250 result on all sent patches. Strange indeed... > > diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > > index aecf7dbe383c..883d399a06a3 100644 > > --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > > +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > > @@ -7,6 +7,10 @@ > > #include "rk3399-sdram-lpddr4-100.dtsi" > > / { > > + config { > > + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; > > I think this is the wrong pin to use. > > The routing of GPIO1_A6 is similar on RK3399 Puma and Pine64 RockPro64, but > it differs massively for the Firefly Roc PC. > > However, a similar routing is done for GPIO1_A5 on the Firefly, I believe > that one is more appropriate. What do you think? I just double-checked the schematics (ROC_3399_PC), looking at signal OTP_OUT_H which is definitely connected to GPIO1_A6 (P26). Also it clearly resets the board when toggled and solves the MMC reset issue I was having on this exact board, so I'm rather confident that it's the right one to use :) Cheers, Paul
Hi Paul, On 9/27/24 11:53 AM, Paul Kocialkowski wrote: > Hi Quentin, > > Thanks for looking into this! > > Le Fri 27 Sep 24, 11:25, Quentin Schulz a écrit : >> I'm not entirely sure on whose side the issue is, but I didn't receive your >> mails, either from the U-Boot mailing list or directly from the Cc field. I >> however could find the patch on lore.kernel.org... and I also received yours >> and Dragan's exchange on patch 4 (but not the patch itself). Any chance you >> received something from my mail server? Does anyone in Cc of this mail >> actually received the mail? > > No automatic reply from your mail server and the logs look good on my side, > with a 250 result on all sent patches. Strange indeed... > >>> diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi >>> index aecf7dbe383c..883d399a06a3 100644 >>> --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi >>> +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi >>> @@ -7,6 +7,10 @@ >>> #include "rk3399-sdram-lpddr4-100.dtsi" >>> / { >>> + config { >>> + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; >> >> I think this is the wrong pin to use. >> >> The routing of GPIO1_A6 is similar on RK3399 Puma and Pine64 RockPro64, but >> it differs massively for the Firefly Roc PC. >> >> However, a similar routing is done for GPIO1_A5 on the Firefly, I believe >> that one is more appropriate. What do you think? > > I just double-checked the schematics (ROC_3399_PC), looking at signal OTP_OUT_H > which is definitely connected to GPIO1_A6 (P26). > > Also it clearly resets the board when toggled and solves the MMC reset issue > I was having on this exact board, so I'm rather confident that it's the right > one to use :) > At least we're on the same page for using OTP_OUT_H, but it's routed to GPIO1_A5 on the schematics I found: https://www.t-firefly.com/download/Firefly-RK3399/hardware/Firefly-RK3399_V10/Firefly-RK3399_V10_SCH_(2017-2-8).pdf Mmmmmm seems like I was looking at the wrong schematics? https://en.t-firefly.com/doc/download/page/id/51.html does route GPIO1_A6 to the OTP_OUT_H signal.. https://en.t-firefly.com/doc/download/page/id/78.html https://en.t-firefly.com/doc/download/page/id/127.html So, the Roc PC, Roc PC Plus and Roc PC Pro all seem to have a similar routing for this pin, therefore: Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Thanks! Quentin
Le Fri 27 Sep 24, 12:07, Quentin Schulz a écrit : > > > > diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > > > > index aecf7dbe383c..883d399a06a3 100644 > > > > --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > > > > +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi > > > > @@ -7,6 +7,10 @@ > > > > #include "rk3399-sdram-lpddr4-100.dtsi" > > > > / { > > > > + config { > > > > + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; > > > > > > I think this is the wrong pin to use. > > > > > > The routing of GPIO1_A6 is similar on RK3399 Puma and Pine64 RockPro64, but > > > it differs massively for the Firefly Roc PC. > > > > > > However, a similar routing is done for GPIO1_A5 on the Firefly, I believe > > > that one is more appropriate. What do you think? > > > > I just double-checked the schematics (ROC_3399_PC), looking at signal OTP_OUT_H > > which is definitely connected to GPIO1_A6 (P26). > > > > Also it clearly resets the board when toggled and solves the MMC reset issue > > I was having on this exact board, so I'm rather confident that it's the right > > one to use :) > > At least we're on the same page for using OTP_OUT_H, but it's routed to > GPIO1_A5 on the schematics I found: > > https://www.t-firefly.com/download/Firefly-RK3399/hardware/Firefly-RK3399_V10/Firefly-RK3399_V10_SCH_(2017-2-8).pdf > > Mmmmmm seems like I was looking at the wrong schematics? Ah yes I think the Firefly-RK3399 and ROC-RK3399-PC are two distinct designs. > https://en.t-firefly.com/doc/download/page/id/51.html does route GPIO1_A6 to > the OTP_OUT_H signal.. > https://en.t-firefly.com/doc/download/page/id/78.html > https://en.t-firefly.com/doc/download/page/id/127.html > > So, the Roc PC, Roc PC Plus and Roc PC Pro all seem to have a similar > routing for this pin, therefore: > > Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Right, and for the record the version I have is the ROC-RK3399-PC Plus. Thanks!
diff --git a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi index aecf7dbe383c..883d399a06a3 100644 --- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi @@ -7,6 +7,10 @@ #include "rk3399-sdram-lpddr4-100.dtsi" / { + config { + sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + vcc_hub_en: vcc_hub_en-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -36,6 +40,10 @@ bootph-pre-ram; }; +&gpio1 { + bootph-pre-ram; +}; + &spi1 { flash@0 { bootph-pre-ram;