diff mbox series

[v1,11/20] arm: socfpga: agilex5: Add SMMU initialization

Message ID 20240920070242.20884-12-tien.fong.chee@intel.com
State Changes Requested
Delegated to: TIEN FONG CHEE
Headers show
Series SoCFPGA: Add Boot Support for Agilex 5 in U-Boot | expand

Commit Message

Chee, Tien Fong Sept. 20, 2024, 7:02 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 34 ++++++++++++++++++++++++
 arch/arm/mach-socfpga/spl_soc64.c        | 17 +++++++++++-
 2 files changed, 50 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index bf30b3b8858..9baf2cbc525 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -387,6 +387,40 @@ 
 				bootph-all;
 			};
 		};
+
+		socfpga_smmu_secure_config: socfpga-smmu-secure-config {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* System manager */
+			i_sys_mgt_sysmgr_csr@10d12000 {
+				reg = <0x10d12000 0x00000500>;
+				intel,offset-settings =
+					/* dma_tbu_stream_ctrl_reg_0_dma0 */
+					<0x0000017c 0x00000000 0x0000003f>,
+					/* dma_tbu_stream_ctrl_reg_0_dma1 */
+					<0x00000180 0x00000000 0x0000003f>,
+					/* sdm_tbu_stream_ctrl_reg_1_sdm */
+					<0x00000184 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_usb2 */
+					<0x00000188 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_sdmmc */
+					<0x00000190 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_nand */
+					<0x00000194 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_etr */
+					<0x00000198 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
+					<0x0000019c 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
+					<0x000001a0 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
+					<0x000001a4 0x00000000 0x0000003f>;
+				bootph-all;
+			};
+		};
 	};
 };
 
diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c
index 4fe67ea0811..3bfe4bb9dd3 100644
--- a/arch/arm/mach-socfpga/spl_soc64.c
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -1,10 +1,12 @@ 
 // SPDX-License-Identifier: GPL-2.0
 /*
- *  Copyright (C) 2020 Intel Corporation. All rights reserved
+ *  Copyright (C) 2020-2024 Intel Corporation. All rights reserved
  *
  */
 
+#include <hang.h>
 #include <spl.h>
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -22,3 +24,16 @@  u32 spl_boot_mode(const u32 boot_device)
 		return MMCSD_MODE_RAW;
 }
 #endif
+
+/* board specific function prior loading SSBL / U-Boot */
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev);
+	if (ret) {
+		printf("HPS SMMU secure settings init failed: %d\n", ret);
+		hang();
+	}
+}