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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434d5272b78sm34941055e9.9.2024.12.04.12.27.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Dec 2024 12:27:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , "Michael S. Tsirkin" , Peter Maydell , Laurent Vivier , Mark Cave-Ayland , Alistair Francis , Anton Johansson , Zhao Liu , "Edgar E. Iglesias" , David Hildenbrand , qemu-s390x@nongnu.org, Max Filippov , Paolo Bonzini , Nicholas Piggin , qemu-arm@nongnu.org, Thomas Huth , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 08/20] target/sh4: Expose CPUSH4State::little_endian property Date: Wed, 4 Dec 2024 21:25:50 +0100 Message-ID: <20241204202602.58083-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241204202602.58083-1-philmd@linaro.org> References: <20241204202602.58083-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org SH4 CPUs endianness is set with an external pin in a power-on reset. Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.h | 6 ++++++ target/sh4/cpu.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d928bcf0067..2502ddba102 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -198,6 +198,12 @@ typedef struct CPUArchState { /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ + /* + * The endian is set with an external pin in a power-on reset. + * The endian cannot be changed dynamically. + */ + bool little_endian; + /* The features that we should emulate. See sh_features above. */ uint32_t features; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcfd..f54005644c9 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -23,6 +23,7 @@ #include "qapi/error.h" #include "qemu/qemu-print.h" #include "cpu.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "exec/exec-all.h" #include "fpu/softfloat-helpers.h" @@ -231,6 +232,12 @@ static void superh_cpu_initfn(Object *obj) env->movcal_backup_tail = &(env->movcal_backup); } +static Property superh_cpu_properties[] = { + DEFINE_PROP_BOOL("little-endian", SuperHCPU, + env.little_endian, !TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + #ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_sh_cpu = { .name = "cpu", @@ -270,6 +277,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, superh_cpu_realizefn, &scc->parent_realize); + device_class_set_props(dc, superh_cpu_properties); resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL, &scc->parent_phases);