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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434d526b158sm36718205e9.8.2024.12.04.12.28.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Dec 2024 12:28:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , "Michael S. Tsirkin" , Peter Maydell , Laurent Vivier , Mark Cave-Ayland , Alistair Francis , Anton Johansson , Zhao Liu , "Edgar E. Iglesias" , David Hildenbrand , qemu-s390x@nongnu.org, Max Filippov , Paolo Bonzini , Nicholas Piggin , qemu-arm@nongnu.org, Thomas Huth , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 15/20] target: Implement CPUClass::datapath_is_big_endian (big-endian) Date: Wed, 4 Dec 2024 21:25:57 +0100 Message-ID: <20241204202602.58083-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241204202602.58083-1-philmd@linaro.org> References: <20241204202602.58083-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org For all targets which have endianness architecturally predefined as big endian (built using TARGET_BIG_ENDIAN=y), their datapath_is_big_endian() handler simply returns %true. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Brian Cain --- target/hexagon/cpu.c | 6 ++++++ target/hppa/cpu.c | 6 ++++++ target/m68k/cpu.c | 6 ++++++ target/openrisc/cpu.c | 6 ++++++ target/s390x/cpu.c | 6 ++++++ 5 files changed, 30 insertions(+) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc490..6407ed80c59 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -245,6 +245,11 @@ void hexagon_debug(CPUHexagonState *env) hexagon_dump(env, stdout, CPU_DUMP_FPU); } +static bool hexagon_cpu_datapath_is_big_endian(CPUState *cs) +{ + return true; +} + static void hexagon_cpu_set_pc(CPUState *cs, vaddr value) { cpu_env(cs)->gpr[HEX_REG_PC] = value; @@ -342,6 +347,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = hexagon_cpu_class_by_name; + cc->datapath_is_big_endian = hexagon_cpu_datapath_is_big_endian; cc->has_work = hexagon_cpu_has_work; cc->dump_state = hexagon_dump_state; cc->set_pc = hexagon_cpu_set_pc; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c38439c1800..8ccd224f2a4 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,6 +203,11 @@ static void hppa_cpu_initfn(Object *obj) cpu_hppa_put_psw(env, PSW_W); } +static bool hppa_cpu_datapath_is_big_endian(CPUState *cs) +{ + return true; +} + static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) { g_autofree char *typename = g_strconcat(cpu_model, "-cpu", NULL); @@ -245,6 +250,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); cc->class_by_name = hppa_cpu_class_by_name; + cc->datapath_is_big_endian = hppa_cpu_datapath_is_big_endian; cc->has_work = hppa_cpu_has_work; cc->mmu_index = hppa_cpu_mmu_index; cc->dump_state = hppa_cpu_dump_state; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558aa..52f8db41d5a 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -24,6 +24,11 @@ #include "migration/vmstate.h" #include "fpu/softfloat.h" +static bool m68k_cpu_datapath_is_big_endian(CPUState *cs) +{ + return true; +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu = M68K_CPU(cs); @@ -571,6 +576,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = m68k_cpu_class_by_name; + cc->datapath_is_big_endian = m68k_cpu_datapath_is_big_endian; cc->has_work = m68k_cpu_has_work; cc->mmu_index = m68k_cpu_mmu_index; cc->dump_state = m68k_cpu_dump_state; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f26..16e39b43ec4 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -25,6 +25,11 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" +static bool openrisc_cpu_datapath_is_big_endian(CPUState *cs) +{ + return true; +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); @@ -257,6 +262,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) &occ->parent_phases); cc->class_by_name = openrisc_cpu_class_by_name; + cc->datapath_is_big_endian = openrisc_cpu_datapath_is_big_endian; cc->has_work = openrisc_cpu_has_work; cc->mmu_index = openrisc_cpu_mmu_index; cc->dump_state = openrisc_cpu_dump_state; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f3010..eda1e3b286f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -44,6 +44,11 @@ #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; +static bool s390_cpu_datapath_is_big_endian(CPUState *cs) +{ + return true; +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { @@ -390,6 +395,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) &scc->parent_phases); cc->class_by_name = s390_cpu_class_by_name, + cc->datapath_is_big_endian = s390_cpu_datapath_is_big_endian; cc->has_work = s390_cpu_has_work; cc->mmu_index = s390x_cpu_mmu_index; cc->dump_state = s390_cpu_dump_state;