Show patches with: State = Action Required       |    Archived = No       |   2384 patches
« 1 2 3 4 … 23 24 »
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
hw/misc/mos6522: Fix bad class definition of the MOS6522 device hw/misc/mos6522: Fix bad class definition of the MOS6522 device - 1 2 - --- 2024-11-14 Thomas Huth New
[24/24] exec: Move 'ram_addr.h' header under sysemu/ namespace exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[23/24] exec/memory: Move qemu_map_ram_ptr() declaration to 'exec/ram_addr.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[22/24] exec/cpu-common: Move ram_addr_t related methods to 'exec/ram_addr.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[21/24] exec: Extract CPU physical memory API to 'sysemu/physmem-target.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[20/24] exec: Declare tlb_vaddr_to_host() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[19/24] exec: Declare tlb_hit*() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[18/24] exec: Declare tlb_flush*() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[17/24] exec: Declare tlb_set_page() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[16/24] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[15/24] exec: Declare tlb_set_page_full() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[14/24] exec: Declare tlb_init/destroy() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[13/24] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[12/24] accel/tcg: Have tlb_vaddr_to_host() use vaddr type exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[11/24] exec: Introduce 'user/guest-host.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[10/24] target/arm/cpu: Restrict cpu_untagged_addr() to user emulation exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[09/24] target/arm/mte: Restrict 'exec/ram_addr.h' to system emulation exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[08/24] linux-user/aarch64/mte: Include missing 'user/abitypes.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[07/24] system/watchpoint: Include missing 'exec/cpu-all.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 1 - --- 2024-11-14 Philippe Mathieu-Daudé New
[06/24] target/rx/cpu: Include missing 'exec/translation-block.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[05/24] target/i386/helper: Include missing 'exec/translation-block.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[04/24] accel/tcg: Include missing 'exec/translation-block.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[03/24] exec/translation-block: Include missing 'exec/vaddr.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[02/24] exec/cpu-defs: Remove unnecessary headers exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 1 --- 2024-11-14 Philippe Mathieu-Daudé New
[01/24] exec/cpu-all: Include missing 'exec/cpu-defs.h' header exec: Build up 'cputlb.h' and 'ram_addr.h' headers - - 2 - --- 2024-11-14 Philippe Mathieu-Daudé New
[v4,2/2] hw/ssi/pnv_spi: Coverity CID 1558827: Use local var seq_index instead of get_seq_index(). hw/ssi/pnv_spi: Remove PnvXferBuffer and fix CID 1558827 - - - - --- 2024-11-12 Chalapathi V New
[v4,1/2] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure hw/ssi/pnv_spi: Remove PnvXferBuffer and fix CID 1558827 - - - - --- 2024-11-12 Chalapathi V New
[v7,1/1] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface) TPM TIS SPI Support - - - - --- 2024-11-10 dan tan New
[v3,17/17] tests/functional: Add microblaze cross-endianness tests hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,16/17] tests/functional: Explicit endianness of microblaze assets hw/microblaze: Allow running cross-endian vCPUs - - 2 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,15/17] hw/microblaze: Support various endianness for s3adsp1800 machines hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,14/17] target/microblaze: Consider endianness while translating code hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,13/17] target/microblaze: Introduce mo_endian() helper hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,12/17] target/microblaze: Set MO_TE once in do_load() / do_store() hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,11/17] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx hw/microblaze: Allow running cross-endian vCPUs - - 2 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,10/17] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors hw/microblaze: Allow running cross-endian vCPUs - - - - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,09/17] hw/ssi/xilinx_spips: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,08/17] hw/ssi/xilinx_spi: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,07/17] hw/char/xilinx_uartlite: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,06/17] hw/timer/xilinx_timer: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[RFC,v3,05/17] hw/timer/xilinx_timer: Allow down to 8-bit memory access hw/microblaze: Allow running cross-endian vCPUs 1 - 2 - --- 2024-11-08 Philippe Mathieu-Daudé New
[RFC,v3,04/17] hw/net/xilinx_ethlite: Simplify by having configurable endianness hw/microblaze: Allow running cross-endian vCPUs - - - - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,03/17] hw/intc/xilinx_intc: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,02/17] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel() hw/microblaze: Allow running cross-endian vCPUs - - 4 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v3,01/17] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-08 Philippe Mathieu-Daudé New
[v2,16/16] tests/functional: Add microblaze cross-endianness tests hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,15/16] tests/functional: Explicit endianness of microblaze assets hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,14/16] hw/microblaze: Support various endianness for s3adsp1800 machines hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,13/16] target/microblaze: Consider endianness while translating code hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,12/16] target/microblaze: Introduce mo_endian() helper hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,11/16] target/microblaze: Set MO_TE once in do_load() / do_store() hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,10/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx hw/microblaze: Allow running cross-endian vCPUs - - 2 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,09/16] hw/ssi/xilinx_spips: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - - - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,08/16] hw/ssi/xilinx_spi: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,07/16] hw/char/xilinx_uartlite: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,06/16] hw/timer/xilinx_timer: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - - - --- 2024-11-07 Philippe Mathieu-Daudé New
[RFC,v2,05/16] hw/timer/xilinx_timer: Allow down to 8-bit memory access hw/microblaze: Allow running cross-endian vCPUs 1 - 2 - --- 2024-11-07 Philippe Mathieu-Daudé New
[RFC,v2,04/16] hw/net/xilinx_ethlite: Simplify by having configurable endianness hw/microblaze: Allow running cross-endian vCPUs - - - - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,03/16] hw/intc/xilinx_intc: Make device endianness configurable hw/microblaze: Allow running cross-endian vCPUs - - - - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,02/16] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel() hw/microblaze: Allow running cross-endian vCPUs - - 3 - --- 2024-11-07 Philippe Mathieu-Daudé New
[v2,01/16] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit hw/microblaze: Allow running cross-endian vCPUs - - 1 - --- 2024-11-07 Philippe Mathieu-Daudé New
[PULL,SUBSYSTEM,qemu-pseries] pseries: Update SLOF firmware image [PULL,SUBSYSTEM,qemu-pseries] pseries: Update SLOF firmware image - - - - --- 2024-11-06 Alexey Kardashevskiy New
tests/functional: Fix the ppc64_hv and the ppc_40p test for read-only assets tests/functional: Fix the ppc64_hv and the ppc_40p test for read-only assets - 1 1 - --- 2024-11-05 Thomas Huth New
[v6,3/3] tests/qtest/tpm: add unit test to tis-spi TPM TIS SPI Support - - - - --- 2024-11-04 dan tan New
[v6,2/3] tpm/tpm_tis_spi: activation for the PowerNV machines TPM TIS SPI Support - - - - --- 2024-11-04 dan tan New
[v6,1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface) TPM TIS SPI Support - - - - --- 2024-11-04 dan tan New
[v5,3/3] tests/qtest/tpm: add unit test to tis-spi TPM TIS SPI Support - - - - --- 2024-11-04 dan tan New
[v5,2/3] tpm/tpm_tis_spi: activation for the PowerNV machines TPM TIS SPI Support - - - - --- 2024-11-04 dan tan New
[v5,1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface) TPM TIS SPI Support - - - - --- 2024-11-04 dan tan New
[PULL,67/67] MAINTAINERS: Remove myself as reviewer [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,66/67] MAINTAINERS: Remove myself from XIVE [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - - - --- 2024-11-04 Nicholas Piggin New
[PULL,65/67] MAINTAINERS: Remove myself from the PowerNV machines [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - - - --- 2024-11-04 Nicholas Piggin New
[PULL,64/67] hw/ppc: Consolidate ppc440 initial mapping creation functions [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 1 --- 2024-11-04 Nicholas Piggin New
[PULL,63/67] hw/ppc: Consolidate e500 initial mapping creation functions [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 1 --- 2024-11-04 Nicholas Piggin New
[PULL,62/67] tests/qtest: Add XIVE tests for the powernv10 machine [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,61/67] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,59/67] pnv/xive: Update PIPR when updating CPPR [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - 1 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,58/67] pnv/xive: Add special handling for pool targets [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,56/67] ppc/xive2: Change context/ring specific functions to be generic [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,55/67] ppc/xive2: Support "Pull Thread Context to Register" operation [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,53/67] ppc/xive2: Dump the VP-group and crowd tables with 'info pic' [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,52/67] ppc/xive2: Dump more NVP state with 'info pic' [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,49/67] pnv/xive2: Define OGEN field in the TIMA [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - - - --- 2024-11-04 Nicholas Piggin New
[PULL,46/67] hw/ppc: Implement -dtb support for PowerNV [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0 [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - - - --- 2024-11-04 Nicholas Piggin New
[PULL,44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0 [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - 1 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,43/67] target/ppc: reduce duplicate code between init_proc_POWER{9, 10} [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,42/67] target/ppc: combine multiple ail checks into one [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,40/67] target/ppc: optimize p7 exception handling routines [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,39/67] target/ppc: optimize p8 exception handling routines [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,38/67] target/ppc: optimize p9 exception handling routines [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 1 - --- 2024-11-04 Nicholas Piggin New
[PULL,37/67] target/ppc: optimize hreg_compute_pmu_hflags_value [PULL,01/67] target/ppc: Set ctx->opcode for decode_insn32() - - 2 - --- 2024-11-04 Nicholas Piggin New
« 1 2 3 4 … 23 24 »