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[220.245.239.57]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-6340a632725sm2691453a12.12.2024.05.10.07.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 07:14:54 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= Subject: [PATCH v2 0/2] ppc/pnv: ADU model for POWER9/10 Date: Sat, 11 May 2024 00:14:43 +1000 Message-ID: <20240510141446.108360-1-npiggin@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::12d; envelope-from=npiggin@gmail.com; helo=mail-il1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org These patches adds the framework for a proper ADU model rather than putting registers into the xscom default ops, and implements ADU's indirect LPC access functionality which IBM's proprietary firmware uses to provide consoles on UARTs. Patch 1 should be quite a simple hooking up the xscom address space. Patch 2 implements one of the memory access functions of the ADU that drives access to LPC address space from XSCOM register operations which is non-trivial but there are similar examples already in tree. Since v1: - Changed to GPL-2.0-or-later - Added an assertion for adu-lpc link - Renamed funcions to pnv_lpc_opb_ prefix rather than pnv_opb_lpc_ - Removed the unnecessary ADU class Thanks, Nick Nicholas Piggin (2): ppc/pnv: Begin a more complete ADU LPC model for POWER9/10 ppc/pnv: Implement ADU access to LPC space include/hw/ppc/pnv_adu.h | 32 ++++++ include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_lpc.h | 5 + include/hw/ppc/pnv_xscom.h | 6 ++ hw/ppc/pnv.c | 20 ++++ hw/ppc/pnv_adu.c | 206 +++++++++++++++++++++++++++++++++++++ hw/ppc/pnv_lpc.c | 12 +-- hw/ppc/pnv_xscom.c | 9 -- hw/ppc/meson.build | 1 + hw/ppc/trace-events | 4 + 10 files changed, 283 insertions(+), 15 deletions(-) create mode 100644 include/hw/ppc/pnv_adu.h create mode 100644 hw/ppc/pnv_adu.c