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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id e65-20020a0dc244000000b0056cffe97a11sm604604ywd.13.2023.06.20.10.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:25:53 -0700 (PDT) From: Joel Upham To: qemu-devel@nongnu.org Cc: Joel Upham , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Marcel Apfelbaum Subject: [PATCH v1 02/23] pc/q35: Apply PCI bus BSEL property for Xen PCI device hotplug Date: Tue, 20 Jun 2023 13:24:36 -0400 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1130; envelope-from=jupham125@gmail.com; helo=mail-yw1-x1130.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 20 Jun 2023 15:45:54 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Q35 we still need to assign BSEL property to bus(es) for PCI device add/hotplug to work. Extend acpi_set_pci_info() function to support Q35 as well. This patch adds new (trivial) function find_q35() which returns root PCIBus object on Q35, in a way similar to what find_i440fx does. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- hw/acpi/pcihp.c | 4 +++- hw/pci-host/q35.c | 9 +++++++++ include/hw/i386/pc.h | 3 +++ 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index cdd6f775a1..f4e39d7a9c 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -40,6 +40,7 @@ #include "qapi/error.h" #include "qom/qom-qobject.h" #include "trace.h" +#include "sysemu/xen.h" #define ACPI_PCIHP_SIZE 0x0018 #define PCI_UP_BASE 0x0000 @@ -84,7 +85,8 @@ static void *acpi_set_bsel(PCIBus *bus, void *opaque) bool is_bridge = IS_PCI_BRIDGE(br); /* hotplugged bridges can't be described in ACPI ignore them */ - if (qbus_is_hotpluggable(BUS(bus))) { + /* Xen requires hotplugging to the root device, even on the Q35 chipset */ + if (qbus_is_hotpluggable(BUS(bus)) || xen_enabled()) { if (!is_bridge || (!br->hotplugged && info->has_bridge_hotplug)) { bus_bsel = g_malloc(sizeof *bus_bsel); diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index fd18920e7f..fe5fc0f47c 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -259,6 +259,15 @@ static void q35_host_initfn(Object *obj) qdev_prop_allow_set_link_before_realize, 0); } +PCIBus *find_q35(void) +{ + PCIHostState *s = OBJECT_CHECK(PCIHostState, + object_resolve_path("/machine/q35", NULL), + TYPE_PCI_HOST_BRIDGE); + return s ? s->bus : NULL; +} + + static const TypeInfo q35_host_info = { .name = TYPE_Q35_HOST_DEVICE, .parent = TYPE_PCIE_HOST_BRIDGE, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index c661e9cc80..550f8fa221 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -196,6 +196,9 @@ void pc_madt_cpu_entry(int uid, const CPUArchIdList *apic_ids, /* sgx.c */ void pc_machine_init_sgx_epc(PCMachineState *pcms); +/* q35.c */ +PCIBus *find_q35(void); + extern GlobalProperty pc_compat_8_0[]; extern const size_t pc_compat_8_0_len;