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[37.6.0.26]) by smtp.gmail.com with ESMTPSA id a10-20020a05600c224a00b003fe23b10fdfsm1798183wmm.36.2023.10.13.00.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 00:58:29 -0700 (PDT) From: Emmanouil Pitsidianakis To: qemu-devel@nongnu.org Cc: Emmanouil Pitsidianakis , Richard Henderson Subject: [RFC PATCH v2 19/78] target/hppa: add fallthrough pseudo-keyword Date: Fri, 13 Oct 2023 10:56:46 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In preparation of raising -Wimplicit-fallthrough to 5, replace all fall-through comments with the fallthrough attribute pseudo-keyword. Signed-off-by: Emmanouil Pitsidianakis --- target/hppa/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9f3ba9f42f..1df81b0fa2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -480,14 +480,14 @@ static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) static void cond_free(DisasCond *cond) { switch (cond->c) { default: cond->a0 = NULL; cond->a1 = NULL; - /* fallthru */ + fallthrough; case TCG_COND_ALWAYS: cond->c = TCG_COND_NEVER; break; case TCG_COND_NEVER: break; } } @@ -3831,65 +3831,65 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) static bool trans_ftest(DisasContext *ctx, arg_ftest *a) { TCGv_reg t; nullify_over(ctx); t = get_temp(ctx); tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); if (a->y == 1) { int mask; bool inv = false; switch (a->c) { case 0: /* simple */ tcg_gen_andi_reg(t, t, 0x4000000); ctx->null_cond = cond_make_0(TCG_COND_NE, t); goto done; case 2: /* rej */ inv = true; - /* fallthru */ + fallthrough; case 1: /* acc */ mask = 0x43ff800; break; case 6: /* rej8 */ inv = true; - /* fallthru */ + fallthrough; case 5: /* acc8 */ mask = 0x43f8000; break; case 9: /* acc6 */ mask = 0x43e0000; break; case 13: /* acc4 */ mask = 0x4380000; break; case 17: /* acc2 */ mask = 0x4200000; break; default: gen_illegal(ctx); return true; } if (inv) { TCGv_reg c = load_const(ctx, mask); tcg_gen_or_reg(t, t, c); ctx->null_cond = cond_make(TCG_COND_EQ, t, c); } else { tcg_gen_andi_reg(t, t, mask); ctx->null_cond = cond_make_0(TCG_COND_EQ, t); } } else { unsigned cbit = (a->y ^ 1) - 1; tcg_gen_extract_reg(t, t, 21 - cbit, 1); ctx->null_cond = cond_make_0(TCG_COND_NE, t); } done: return nullify_end(ctx); } /* * Float class 2 */ @@ -4219,28 +4219,28 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); - /* FALLTHRU */ + fallthrough; case DISAS_IAQ_N_UPDATED: if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { tcg_gen_lookup_and_goto_ptr(); break; } - /* FALLTHRU */ + fallthrough; case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; default: g_assert_not_reached(); } }