From patchwork Fri Mar 19 20:02:02 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 48190 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E5C02B7067 for ; Sat, 20 Mar 2010 07:43:46 +1100 (EST) Received: from localhost ([127.0.0.1]:60492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NsirQ-0003g7-Mu for incoming@patchwork.ozlabs.org; Fri, 19 Mar 2010 16:32:00 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nsil6-0001gm-QO for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:28 -0400 Received: from [199.232.76.173] (port=60619 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nsil6-0001gR-A1 for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:28 -0400 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Nsil0-0002M3-T5 for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:28 -0400 Received: from are.twiddle.net ([75.149.56.221]:59909) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Nsikz-0002LL-F4 for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:21 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id D3F68B0D; Fri, 19 Mar 2010 13:25:17 -0700 (PDT) Message-Id: In-Reply-To: References: From: Richard Henderson Date: Fri, 19 Mar 2010 13:02:02 -0700 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 7/9] tcg: Allow target-specific implementation of EQV. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/README | 2 +- tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/ppc64/tcg-target.h | 2 ++ tcg/s390/tcg-target.h | 2 ++ tcg/sparc/tcg-target.h | 2 ++ tcg/tcg-op.h | 11 +++++++++++ tcg/tcg-opc.h | 6 ++++++ tcg/x86_64/tcg-target.h | 2 ++ 11 files changed, 30 insertions(+), 1 deletions(-) diff --git a/tcg/README b/tcg/README index 43f769a..c0e998c 100644 --- a/tcg/README +++ b/tcg/README @@ -208,7 +208,7 @@ t0=t1&~t2 * eqv_i32/i64 t0, t1, t2 -t0=~(t1^t2) +t0=~(t1^t2), or equivalently, t0=t1^~t2 * nand_i32/i64 t0, t1, t2 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 4cad967..57a9189 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -67,6 +67,7 @@ enum { // #define TCG_TARGET_HAS_rot_i32 #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 +// #define TCG_TARGET_HAS_eqv_i32 #define TCG_TARGET_HAS_GUEST_BASE diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index e994fd5..1356ce9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -57,6 +57,7 @@ enum { #define TCG_TARGET_HAS_not_i32 // #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 +// #define TCG_TARGET_HAS_eqv_i32 #define TCG_TARGET_HAS_GUEST_BASE diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 377b0c8..97256a5 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -87,6 +87,7 @@ enum { #undef TCG_TARGET_HAS_bswap16_i32 #undef TCG_TARGET_HAS_andc_i32 #undef TCG_TARGET_HAS_orc_i32 +#undef TCG_TARGET_HAS_eqv_i32 /* optional instructions automatically implemented */ #undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */ diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 0c71a11..d2c6fd2 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -89,6 +89,7 @@ enum { #define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_andc_i32 #define TCG_TARGET_HAS_orc_i32 +/* #define TCG_TARGET_HAS_eqv_i32 */ #define TCG_AREG0 TCG_REG_R27 #define TCG_AREG1 TCG_REG_R24 diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index f5de642..51280af 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -80,6 +80,7 @@ enum { #define TCG_TARGET_HAS_neg_i32 /* #define TCG_TARGET_HAS_andc_i32 */ /* #define TCG_TARGET_HAS_orc_i32 */ +/* #define TCG_TARGET_HAS_eqv_i32 */ #define TCG_TARGET_HAS_div_i64 /* #define TCG_TARGET_HAS_rot_i64 */ @@ -96,6 +97,7 @@ enum { #define TCG_TARGET_HAS_neg_i64 /* #define TCG_TARGET_HAS_andc_i64 */ /* #define TCG_TARGET_HAS_orc_i64 */ +/* #define TCG_TARGET_HAS_eqv_i64 */ #define TCG_AREG0 TCG_REG_R27 #define TCG_AREG1 TCG_REG_R24 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index e803401..bf8e80b 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -59,6 +59,7 @@ enum { // #define TCG_TARGET_HAS_neg_i32 // #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 +// #define TCG_TARGET_HAS_eqv_i32 // #define TCG_TARGET_HAS_div_i64 // #define TCG_TARGET_HAS_rot_i64 @@ -75,6 +76,7 @@ enum { // #define TCG_TARGET_HAS_neg_i64 // #define TCG_TARGET_HAS_andc_i64 // #define TCG_TARGET_HAS_orc_i64 +// #define TCG_TARGET_HAS_eqv_i64 /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R15 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index dbc574d..175abc5 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -100,6 +100,7 @@ enum { #define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_andc_i32 #define TCG_TARGET_HAS_orc_i32 +// #define TCG_TARGET_HAS_eqv_i32 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_div_i64 @@ -117,6 +118,7 @@ enum { #define TCG_TARGET_HAS_not_i64 #define TCG_TARGET_HAS_andc_i64 #define TCG_TARGET_HAS_orc_i64 +// #define TCG_TARGET_HAS_eqv_i64 #endif /* Note: must be synced with dyngen-exec.h and Makefile.target */ diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index dc81f3e..63bf614 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1740,14 +1740,25 @@ static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_eqv_i32 + tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2); +#else tcg_gen_xor_i32(ret, arg1, arg2); tcg_gen_not_i32(ret, ret); +#endif } static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_eqv_i64 + tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2); +#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32 + tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#else tcg_gen_xor_i64(ret, arg1, arg2); tcg_gen_not_i64(ret, ret); +#endif } static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index d232695..a723b3c 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -114,6 +114,9 @@ DEF2(andc_i32, 1, 2, 0, 0) #ifdef TCG_TARGET_HAS_orc_i32 DEF2(orc_i32, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_eqv_i32 +DEF2(eqv_i32, 1, 2, 0, 0) +#endif #if TCG_TARGET_REG_BITS == 64 DEF2(mov_i64, 1, 1, 0, 0) @@ -196,6 +199,9 @@ DEF2(andc_i64, 1, 2, 0, 0) #ifdef TCG_TARGET_HAS_orc_i64 DEF2(orc_i64, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_eqv_i64 +DEF2(eqv_i64, 1, 2, 0, 0) +#endif #endif /* QEMU specific */ diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index d1e8b9e..2951fcd 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -84,6 +84,8 @@ enum { // #define TCG_TARGET_HAS_andc_i64 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_orc_i64 +// #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_eqv_i64 #define TCG_TARGET_HAS_GUEST_BASE