[7/9] tcg: Allow target-specific implementation of EQV.

diff --git a/tcg/README b/tcg/README
index 43f769a..c0e998c 100644
--- a/tcg/README
+++ b/tcg/README
@@ -208,7 +208,7 @@  t0=t1&~t2
 
 * eqv_i32/i64 t0, t1, t2
 
-t0=~(t1^t2)
+t0=~(t1^t2), or equivalently, t0=t1^~t2
 
 * nand_i32/i64 t0, t1, t2
 
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 4cad967..57a9189 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -67,6 +67,7 @@  enum {
 // #define TCG_TARGET_HAS_rot_i32
 #define TCG_TARGET_HAS_andc_i32
 // #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
 
 #define TCG_TARGET_HAS_GUEST_BASE
 
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index e994fd5..1356ce9 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -57,6 +57,7 @@  enum {
 #define TCG_TARGET_HAS_not_i32
 // #define TCG_TARGET_HAS_andc_i32
 // #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
 
 #define TCG_TARGET_HAS_GUEST_BASE
 
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 377b0c8..97256a5 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -87,6 +87,7 @@  enum {
 #undef TCG_TARGET_HAS_bswap16_i32
 #undef TCG_TARGET_HAS_andc_i32
 #undef TCG_TARGET_HAS_orc_i32
+#undef TCG_TARGET_HAS_eqv_i32
 
 /* optional instructions automatically implemented */
 #undef TCG_TARGET_HAS_neg_i32      /* sub  rd, zero, rt   */
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 0c71a11..d2c6fd2 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -89,6 +89,7 @@  enum {
 #define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_andc_i32
 #define TCG_TARGET_HAS_orc_i32
+/* #define TCG_TARGET_HAS_eqv_i32 */
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index f5de642..51280af 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -80,6 +80,7 @@  enum {
 #define TCG_TARGET_HAS_neg_i32
 /* #define TCG_TARGET_HAS_andc_i32 */
 /* #define TCG_TARGET_HAS_orc_i32 */
+/* #define TCG_TARGET_HAS_eqv_i32 */
 
 #define TCG_TARGET_HAS_div_i64
 /* #define TCG_TARGET_HAS_rot_i64 */
@@ -96,6 +97,7 @@  enum {
 #define TCG_TARGET_HAS_neg_i64
 /* #define TCG_TARGET_HAS_andc_i64 */
 /* #define TCG_TARGET_HAS_orc_i64 */
+/* #define TCG_TARGET_HAS_eqv_i64 */
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index e803401..bf8e80b 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -59,6 +59,7 @@  enum {
 // #define TCG_TARGET_HAS_neg_i32
 // #define TCG_TARGET_HAS_andc_i32
 // #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
 
 // #define TCG_TARGET_HAS_div_i64
 // #define TCG_TARGET_HAS_rot_i64
@@ -75,6 +76,7 @@  enum {
 // #define TCG_TARGET_HAS_neg_i64
 // #define TCG_TARGET_HAS_andc_i64
 // #define TCG_TARGET_HAS_orc_i64
+// #define TCG_TARGET_HAS_eqv_i64
 
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R15
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index dbc574d..175abc5 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -100,6 +100,7 @@  enum {
 #define TCG_TARGET_HAS_not_i32
 #define TCG_TARGET_HAS_andc_i32
 #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_eqv_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_div_i64
@@ -117,6 +118,7 @@  enum {
 #define TCG_TARGET_HAS_not_i64
 #define TCG_TARGET_HAS_andc_i64
 #define TCG_TARGET_HAS_orc_i64
+// #define TCG_TARGET_HAS_eqv_i64
 #endif
 
 /* Note: must be synced with dyngen-exec.h and Makefile.target */
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index dc81f3e..63bf614 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1740,14 +1740,25 @@  static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_eqv_i32
+    tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
+#else
     tcg_gen_xor_i32(ret, arg1, arg2);
     tcg_gen_not_i32(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_eqv_i64
+    tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     tcg_gen_xor_i64(ret, arg1, arg2);
     tcg_gen_not_i64(ret, ret);
+#endif
 }
 
 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index d232695..a723b3c 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -114,6 +114,9 @@  DEF2(andc_i32, 1, 2, 0, 0)
 #ifdef TCG_TARGET_HAS_orc_i32
 DEF2(orc_i32, 1, 2, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_eqv_i32
+DEF2(eqv_i32, 1, 2, 0, 0)
+#endif
 
 #if TCG_TARGET_REG_BITS == 64
 DEF2(mov_i64, 1, 1, 0, 0)
@@ -196,6 +199,9 @@  DEF2(andc_i64, 1, 2, 0, 0)
 #ifdef TCG_TARGET_HAS_orc_i64
 DEF2(orc_i64, 1, 2, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_eqv_i64
+DEF2(eqv_i64, 1, 2, 0, 0)
+#endif
 #endif
 
 /* QEMU specific */
diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
index d1e8b9e..2951fcd 100644
--- a/tcg/x86_64/tcg-target.h
+++ b/tcg/x86_64/tcg-target.h
@@ -84,6 +84,8 @@  enum {
 // #define TCG_TARGET_HAS_andc_i64
 // #define TCG_TARGET_HAS_orc_i32
 // #define TCG_TARGET_HAS_orc_i64
+// #define TCG_TARGET_HAS_eqv_i32
+// #define TCG_TARGET_HAS_eqv_i64
 
 #define TCG_TARGET_HAS_GUEST_BASE