From patchwork Fri Mar 19 20:03:58 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 48191 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6F117B7D12 for ; Sat, 20 Mar 2010 07:46:12 +1100 (EST) Received: from localhost ([127.0.0.1]:32844 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nsit6-00040j-4G for incoming@patchwork.ozlabs.org; Fri, 19 Mar 2010 16:33:44 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nsil8-0001hZ-8D for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:30 -0400 Received: from [199.232.76.173] (port=60620 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nsil7-0001h5-8B for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:29 -0400 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Nsil0-0002M9-Vg for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:29 -0400 Received: from are.twiddle.net ([75.149.56.221]:59908) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Nsikz-0002LJ-DB for qemu-devel@nongnu.org; Fri, 19 Mar 2010 16:25:21 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id DCABAB0E; Fri, 19 Mar 2010 13:25:17 -0700 (PDT) Message-Id: In-Reply-To: References: From: Richard Henderson Date: Fri, 19 Mar 2010 13:03:58 -0700 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 8/9] tcg: Allow target-specific implementation of NAND. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 1 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.h | 1 + tcg/ppc64/tcg-target.h | 2 ++ tcg/s390/tcg-target.h | 2 ++ tcg/sparc/tcg-target.h | 2 ++ tcg/tcg-op.h | 11 +++++++++++ tcg/tcg-opc.h | 6 ++++++ tcg/x86_64/tcg-target.h | 2 ++ 10 files changed, 29 insertions(+), 0 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 57a9189..0e8e1cc 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -68,6 +68,7 @@ enum { #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 #define TCG_TARGET_HAS_GUEST_BASE diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 1356ce9..8e7ed11 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -58,6 +58,7 @@ enum { // #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 #define TCG_TARGET_HAS_GUEST_BASE diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 97256a5..179151c 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -88,6 +88,7 @@ enum { #undef TCG_TARGET_HAS_andc_i32 #undef TCG_TARGET_HAS_orc_i32 #undef TCG_TARGET_HAS_eqv_i32 +#undef TCG_TARGET_HAS_nand_i32 /* optional instructions automatically implemented */ #undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */ diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d2c6fd2..1087c00 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -90,6 +90,7 @@ enum { #define TCG_TARGET_HAS_andc_i32 #define TCG_TARGET_HAS_orc_i32 /* #define TCG_TARGET_HAS_eqv_i32 */ +/* #define TCG_TARGET_HAS_nand_i32 */ #define TCG_AREG0 TCG_REG_R27 #define TCG_AREG1 TCG_REG_R24 diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 51280af..acd1f57 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -81,6 +81,7 @@ enum { /* #define TCG_TARGET_HAS_andc_i32 */ /* #define TCG_TARGET_HAS_orc_i32 */ /* #define TCG_TARGET_HAS_eqv_i32 */ +/* #define TCG_TARGET_HAS_nand_i32 */ #define TCG_TARGET_HAS_div_i64 /* #define TCG_TARGET_HAS_rot_i64 */ @@ -98,6 +99,7 @@ enum { /* #define TCG_TARGET_HAS_andc_i64 */ /* #define TCG_TARGET_HAS_orc_i64 */ /* #define TCG_TARGET_HAS_eqv_i64 */ +/* #define TCG_TARGET_HAS_nand_i64 */ #define TCG_AREG0 TCG_REG_R27 #define TCG_AREG1 TCG_REG_R24 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index bf8e80b..b0d2866 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -60,6 +60,7 @@ enum { // #define TCG_TARGET_HAS_andc_i32 // #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 // #define TCG_TARGET_HAS_div_i64 // #define TCG_TARGET_HAS_rot_i64 @@ -77,6 +78,7 @@ enum { // #define TCG_TARGET_HAS_andc_i64 // #define TCG_TARGET_HAS_orc_i64 // #define TCG_TARGET_HAS_eqv_i64 +// #define TCG_TARGET_HAS_nand_i64 /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R15 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 175abc5..b0b6c94 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -101,6 +101,7 @@ enum { #define TCG_TARGET_HAS_andc_i32 #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_eqv_i32 +// #define TCG_TARGET_HAS_nand_i32 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_div_i64 @@ -119,6 +120,7 @@ enum { #define TCG_TARGET_HAS_andc_i64 #define TCG_TARGET_HAS_orc_i64 // #define TCG_TARGET_HAS_eqv_i64 +// #define TCG_TARGET_HAS_nand_i64 #endif /* Note: must be synced with dyngen-exec.h and Makefile.target */ diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 63bf614..7bd498d 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1763,14 +1763,25 @@ static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { +#ifdef TCG_TARGET_HAS_nand_i32 + tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2); +#else tcg_gen_and_i32(ret, arg1, arg2); tcg_gen_not_i32(ret, ret); +#endif } static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { +#ifdef TCG_TARGET_HAS_nand_i64 + tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2); +#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32 + tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2)); + tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); +#else tcg_gen_and_i64(ret, arg1, arg2); tcg_gen_not_i64(ret, ret); +#endif } static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index a723b3c..37ff0eb 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -117,6 +117,9 @@ DEF2(orc_i32, 1, 2, 0, 0) #ifdef TCG_TARGET_HAS_eqv_i32 DEF2(eqv_i32, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_nand_i32 +DEF2(nand_i32, 1, 2, 0, 0) +#endif #if TCG_TARGET_REG_BITS == 64 DEF2(mov_i64, 1, 1, 0, 0) @@ -202,6 +205,9 @@ DEF2(orc_i64, 1, 2, 0, 0) #ifdef TCG_TARGET_HAS_eqv_i64 DEF2(eqv_i64, 1, 2, 0, 0) #endif +#ifdef TCG_TARGET_HAS_nand_i64 +DEF2(nand_i64, 1, 2, 0, 0) +#endif #endif /* QEMU specific */ diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 2951fcd..119b50a 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -86,6 +86,8 @@ enum { // #define TCG_TARGET_HAS_orc_i64 // #define TCG_TARGET_HAS_eqv_i32 // #define TCG_TARGET_HAS_eqv_i64 +// #define TCG_TARGET_HAS_nand_i32 +// #define TCG_TARGET_HAS_nand_i64 #define TCG_TARGET_HAS_GUEST_BASE