From patchwork Wed Sep 30 21:09:35 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 34881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 26778B7BEA for ; Sat, 3 Oct 2009 05:57:34 +1000 (EST) Received: from localhost ([127.0.0.1]:56963 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MtoFv-0002d6-Oy for incoming@patchwork.ozlabs.org; Fri, 02 Oct 2009 15:57:31 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MtoB0-0005Tg-Aj for qemu-devel@nongnu.org; Fri, 02 Oct 2009 15:52:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MtoAz-0005Rf-A1 for qemu-devel@nongnu.org; Fri, 02 Oct 2009 15:52:25 -0400 Received: from [199.232.76.173] (port=42353 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MtoAz-0005R2-1O for qemu-devel@nongnu.org; Fri, 02 Oct 2009 15:52:25 -0400 Received: from hall.aurel32.net ([88.191.82.174]:40565) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MtoAy-0003Cu-Dk for qemu-devel@nongnu.org; Fri, 02 Oct 2009 15:52:24 -0400 Received: from [2002:52e8:2fb:1:21e:8cff:feb0:693b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1MtoAt-0004u7-5e for qemu-devel@nongnu.org; Fri, 02 Oct 2009 21:52:19 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.69) (envelope-from ) id 1MtoAr-00023s-DJ for qemu-devel@nongnu.org; Fri, 02 Oct 2009 21:52:17 +0200 Resent-From: Aurelien Jarno Resent-Date: Fri, 2 Oct 2009 21:52:17 +0200 Resent-Message-ID: <20091002195217.GA7454@volta.aurel32.net> Resent-To: qemu-devel@nongnu.org Message-Id: From: Aurelien Jarno Date: Wed, 30 Sep 2009 23:09:35 +0200 Resent-Date: Fri, 02 Oct 2009 21:52:17 +0200 X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 3) Subject: [Qemu-devel] [PATCH 1/3] tcg: add ext{8,16,32}u_i{32,64} TCG ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Currently zero extensions ops are implemented by a and op with a constant. This is then catched in some backend, and replaced by a zero extension instruction. While this works well on RISC machines, this adds a useless register move on non-RISC machines. Example on x86: ext16u_i32 r1, r2 is translated into mov %eax,%ebx movzwl %bx, %ebx while the optimized version should be: movzwl %ax, %ebx This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be implemented in the backends to avoid emitting useless register moves. Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 24 +++++++++++++++++++++--- tcg/tcg-opc.h | 15 +++++++++++++++ 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 7cb6934..faf2e8b 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1189,16 +1189,22 @@ static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg) #endif } -/* These are currently just for convenience. - We assume a target will recognise these automatically . */ static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg) { +#ifdef TCG_TARGET_HAS_ext8u_i32 + tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg); +#else tcg_gen_andi_i32(ret, arg, 0xffu); +#endif } static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) { +#ifdef TCG_TARGET_HAS_ext16u_i32 + tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg); +#else tcg_gen_andi_i32(ret, arg, 0xffffu); +#endif } /* Note: we assume the two high bytes are set to zero */ @@ -1358,17 +1364,29 @@ static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg) static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg) { +#ifdef TCG_TARGET_HAS_ext8u_i64 + tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg); +#else tcg_gen_andi_i64(ret, arg, 0xffu); +#endif } static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg) { +#ifdef TCG_TARGET_HAS_ext16u_i64 + tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg); +#else tcg_gen_andi_i64(ret, arg, 0xffffu); +#endif } static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg) { +#ifdef TCG_TARGET_HAS_ext32u_i64 + tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg); +#else tcg_gen_andi_i64(ret, arg, 0xffffffffu); +#endif } /* Note: we assume the target supports move between 32 and 64 bit @@ -1382,7 +1400,7 @@ static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg) registers */ static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg) { - tcg_gen_andi_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)), 0xffffffffu); + tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg))); } /* Note: we assume the target supports move between 32 and 64 bit diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 3a095fc..b7f3fd7 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -89,6 +89,12 @@ DEF2(ext8s_i32, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_ext16s_i32 DEF2(ext16s_i32, 1, 1, 0, 0) #endif +#ifdef TCG_TARGET_HAS_ext8u_i32 +DEF2(ext8u_i32, 1, 1, 0, 0) +#endif +#ifdef TCG_TARGET_HAS_ext16u_i32 +DEF2(ext16u_i32, 1, 1, 0, 0) +#endif #ifdef TCG_TARGET_HAS_bswap16_i32 DEF2(bswap16_i32, 1, 1, 0, 0) #endif @@ -152,6 +158,15 @@ DEF2(ext16s_i64, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_ext32s_i64 DEF2(ext32s_i64, 1, 1, 0, 0) #endif +#ifdef TCG_TARGET_HAS_ext8u_i64 +DEF2(ext8u_i64, 1, 1, 0, 0) +#endif +#ifdef TCG_TARGET_HAS_ext16u_i64 +DEF2(ext16u_i64, 1, 1, 0, 0) +#endif +#ifdef TCG_TARGET_HAS_ext32u_i64 +DEF2(ext32u_i64, 1, 1, 0, 0) +#endif #ifdef TCG_TARGET_HAS_bswap16_i64 DEF2(bswap16_i64, 1, 1, 0, 0) #endif