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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id e65-20020a0dc244000000b0056cffe97a11sm604604ywd.13.2023.06.20.10.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:26:23 -0700 (PDT) From: Joel Upham To: qemu-devel@nongnu.org Cc: Joel Upham , Stefano Stabellini , Anthony Perard , Paul Durrant , xen-devel@lists.xenproject.org (open list:X86 Xen CPUs) Subject: [PATCH v1 14/23] xen/pt: add fixed-size PCIe Extended Capabilities descriptors Date: Tue, 20 Jun 2023 13:24:48 -0400 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1133; envelope-from=jupham125@gmail.com; helo=mail-yw1-x1133.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 20 Jun 2023 15:45:55 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds description structures for all fixed-size PCIe Extended Capabilities. For every capability register group, only 2 registers are emulated currently: Capability ID (16 bit) and Next Capability Offset/Version (16 bit). Both needed to implement selective capability hiding. All other registers are passed through at the moment (unless they belong to a "hardwired" capability which is hidden) Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- hw/xen/xen_pt_config_init.c | 183 ++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c index 20b5561d25..69d8857c66 100644 --- a/hw/xen/xen_pt_config_init.c +++ b/hw/xen/xen_pt_config_init.c @@ -1669,6 +1669,37 @@ static XenPTRegInfo xen_pt_ext_cap_emu_reg_vendor[] = { .size = 0, }, }; + +/* Common reg static information table for all passthru-type + * PCIe Extended Capabilities. Only Extended Cap ID and + * Next pointer are handled (to support capability hiding). + */ +static XenPTRegInfo xen_pt_ext_cap_emu_reg_dummy[] = { + { + .offset = XEN_PCIE_CAP_ID, + .size = 2, + .init_val = 0x0000, + .ro_mask = 0xFFFF, + .emu_mask = 0xFFFF, + .init = xen_pt_ext_cap_capid_reg_init, + .u.w.read = xen_pt_word_reg_read, + .u.w.write = xen_pt_word_reg_write, + }, + { + .offset = XEN_PCIE_CAP_LIST_NEXT, + .size = 2, + .init_val = 0x0000, + .ro_mask = 0xFFFF, + .emu_mask = 0xFFFF, + .init = xen_pt_ext_cap_ptr_reg_init, + .u.w.read = xen_pt_word_reg_read, + .u.w.write = xen_pt_word_reg_write, + }, + { + .size = 0, + }, +}; + /**************************** * Capabilities */ @@ -1945,6 +1976,158 @@ static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { .size_init = xen_pt_ext_cap_vendor_size_init, .emu_regs = xen_pt_ext_cap_emu_reg_vendor, }, + /* Device Serial Number Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_DSN), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_DSN_SIZEOF, /*0x0C*/ + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Power Budgeting Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PWR), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_PWR_SIZEOF, /*0x10*/ + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Root Complex Internal Link Control Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCILC), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x0C, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Root Complex Event Collector Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCEC), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x08, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Root Complex Register Block Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_RCRB), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x14, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Configuration Access Correlation Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_CAC), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x08, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Alternate Routing ID Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ARI), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_ARI_SIZEOF, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Address Translation Services Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_ATS), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_ATS_SIZEOF, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Single Root I/O Virtualization Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_SRIOV), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_SRIOV_SIZEOF, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Page Request Interface Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PRI), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_PRI_SIZEOF, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Latency Tolerance Reporting Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_LTR), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_LTR_SIZEOF, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Secondary PCIe Capability Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_SECPCI), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x10, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Process Address Space ID Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PASID), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = PCI_EXT_CAP_PASID_SIZEOF, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* L1 PM Substates Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_L1SS), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x10, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Precision Time Measurement Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(PCI_EXT_CAP_ID_PTM), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x0C, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* M-PCIe Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(0x20), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x1C, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* LN Requester (LNR) Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(0x1C), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x08, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Function Readiness Status (FRS) Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(0x21), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x10, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, + /* Readiness Time Extended Capability reg group */ + { + .grp_id = PCIE_EXT_CAP_ID(0x22), + .grp_type = XEN_PT_GRP_TYPE_EMU, + .grp_size = 0x0C, + .size_init = xen_pt_reg_grp_size_init, + .emu_regs = xen_pt_ext_cap_emu_reg_dummy, + }, { .grp_size = 0, },