From patchwork Thu Jun 26 05:02:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 364242 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 19B4A1400B5 for ; Thu, 26 Jun 2014 15:05:33 +1000 (EST) Received: from localhost ([::1]:42291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01sJ-0005Qj-AB for incoming@patchwork.ozlabs.org; Thu, 26 Jun 2014 01:05:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01pW-0000Ys-KP for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X01pQ-0006pL-Km for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:38 -0400 Received: from mail-ig0-x231.google.com ([2607:f8b0:4001:c05::231]:36615) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01pQ-0006pB-G0 for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:32 -0400 Received: by mail-ig0-f177.google.com with SMTP id c1so286908igq.16 for ; Wed, 25 Jun 2014 22:02:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=M+aWufsS/gx62R0cvIIkjmBZwAGvv0kf3lcj63KKbHY=; b=IodHc2HZVNHvbWLwkruxDwB4Qkuppe1uR+/HE7iowiOUF/IDE+Ho5vRo47MDwJ3J+m I7eF2nuFPwe5C3zYhYiWhdf9Vb2LOmgi4u95bTdtALVBI8HkZqO+/dL4PtWJCGVLFj3t dVnJZbhiNelawO23uE2NqyRV0fXlW3xxWrz2kzLUHtWbshDPgFLR/RfBB5UmT1/xVzlh cZorKZENuBJ+xSxTn4BQkfa5WQox2OQSVYLXqZXK9QNm22d7oE5It4lXrlFrznWzwGeA 22Izx1BkgLMc0jjuaYi8YIce6xfE2R3ANWmMbjFzkERZp8kTh1/UuxMocHcOi4onmws6 Jjqg== X-Received: by 10.43.39.137 with SMTP id tm9mr11133591icb.41.1403758951936; Wed, 25 Jun 2014 22:02:31 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id ci7sm1067503igb.11.2014.06.25.22.02.28 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Wed, 25 Jun 2014 22:02:31 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Thu, 26 Jun 2014 15:02:25 +1000 Message-Id: X-Mailer: git-send-email 1.9.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c05::231 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, cov@codeaurora.org, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v2 4/7] target-arm: Implement pmccntr_sync function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This is used to synchronise the PMCCNTR counter and swap its state between enabled and disabled if required. It must always be called twice, both before and after any logic that could change the state of the PMCCNTR counter. Signed-off-by: Alistair Francis --- Remembering that the c15_ccnt register stores the last time the counter was reset if enabled. If disabled it stores the counter value (when it was disabled). The three use cases are as below: -- Starts enabled/disabled and is staying enabled/disabled -- The two calls to pmccntr_sync cancel each other out. Each call implements this logic: env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt Which expands to: env->cp15.c15_ccnt = temp_ticks - (temp_ticks - env->cp15.c15_ccnt) env->cp15.c15_ccnt = env->cp15.c15_ccnt -- Starts enabled, gets disabled -- The logic is run during the first call while during the second call it is not. That means that c15_ccnt changes from storing the last time the counter was reset, to storing the absolute value of the counter. -- Starts disabled, gets enabled -- During the fist call no changes are made, while during the second call the register is changed. This changes it from storing the absolute value to storing the last time the counter was reset. target-arm/cpu.h | 11 +++++++++++ target-arm/helper.c | 19 +++++++++++++++++++ 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6a2efd8..fc1a70d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1032,6 +1032,17 @@ static inline bool cp_access_ok(int current_pl, } /** + * pmccntr_sync + * @cpu: ARMCPU + * + * Syncronises the counter in the PMCCNTR. This must always be called twice, + * once before any action that might effect the timer and again afterwards. + * The function is used to swap the state of the register if required. + * This only happens when not in user mode (!CONFIG_USER_ONLY) + */ +void pmccntr_sync(CPUARMState *env); + +/** * write_list_to_cpustate * @cpu: ARMCPU * diff --git a/target-arm/helper.c b/target-arm/helper.c index 141e252..016fe47 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -586,6 +586,25 @@ static bool arm_ccnt_enabled(CPUARMState *env) } #endif +void pmccntr_sync(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + uint64_t temp_ticks; + + temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), + get_ticks_per_sec(), 1000000); + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + temp_ticks /= 64; + } + + if (arm_ccnt_enabled(env)) { + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; + } +#endif +} + #ifndef CONFIG_USER_ONLY static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)