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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id e65-20020a0dc244000000b0056cffe97a11sm604604ywd.13.2023.06.20.10.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:26:18 -0700 (PDT) From: Joel Upham To: qemu-devel@nongnu.org Cc: Joel Upham , Stefano Stabellini , Anthony Perard , Paul Durrant , xen-devel@lists.xenproject.org (open list:X86 Xen CPUs) Subject: [PATCH v1 12/23] xen/pt: allow to hide PCIe Extended Capabilities Date: Tue, 20 Jun 2023 13:24:46 -0400 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1134; envelope-from=jupham125@gmail.com; helo=mail-yw1-x1134.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 20 Jun 2023 15:45:54 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We need to hide some unwanted PCI/PCIe capabilities for passed through devices. Normally we do this by marking the capability register group as XEN_PT_GRP_TYPE_HARDWIRED which exclude this capability from the capability list and returns zeroes on attempts to read capability body. Skipping the capability in the linked list of capabilities can be done by changing Next Capability register to skip one or many unwanted capabilities. One difference between PCI and PCIe Extended capabilities is that we don't have the list head field anymore. PCIe Extended capabilities always start at offset 0x100 if they're present. Unfortunately, there are typically only few PCIe extended capabilities present which means there is a chance that some capability we want to hide will reside at offset 0x100 in PCIe config space. The simplest way to hide such capabilities from guest OS or drivers is faking their capability ID value. This patch adds the Capability ID register handler which checks - if the capability to which this register belong starts at offset 0x100 in PCIe config space - if this capability is marked as XEN_PT_GRP_TYPE_HARDWIRED If it is the case, then a fake Capability ID value is returned. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- hw/xen/xen_pt.c | 11 ++++++++++- hw/xen/xen_pt.h | 4 ++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index f757978800..2399fabb2b 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -164,7 +164,16 @@ static uint32_t xen_pt_pci_read_config(PCIDevice *d, uint32_t addr, int len) reg_grp_entry = xen_pt_find_reg_grp(s, addr); if (reg_grp_entry) { /* check 0-Hardwired register group */ - if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) { + if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED && + /* + * For PCIe Extended Capabilities we need to emulate + * CapabilityID and NextCapability/Version registers for a + * hardwired reg group located at the offset 0x100 in PCIe + * config space. This allows us to hide the first extended + * capability as well. + */ + !(reg_grp_entry->base_offset == PCI_CONFIG_SPACE_SIZE && + ranges_overlap(addr, len, 0x100, 4))) { /* no need to emulate, just return 0 */ val = 0; goto exit; diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h index eb062be3f4..9a191cbc8f 100644 --- a/hw/xen/xen_pt.h +++ b/hw/xen/xen_pt.h @@ -93,6 +93,10 @@ typedef int (*xen_pt_conf_byte_read) #define XEN_PCI_INTEL_OPREGION 0xfc +#define XEN_PCIE_CAP_ID 0 +#define XEN_PCIE_CAP_LIST_NEXT 2 +#define XEN_PCIE_FAKE_CAP_ID_BASE 0xFE00 + #define XEN_PCI_IGD_DOMAIN 0 #define XEN_PCI_IGD_BUS 0 #define XEN_PCI_IGD_DEV 2