diff mbox series

[38/43] target/ppc/mmu-hash32.c: Use pte address as parameter instead of offset

Message ID c2365f41612f7898ab57a4a85e1028eba3a5244b.1716763435.git.balaton@eik.bme.hu
State New
Headers show
Series Remaining MMU clean up patches | expand

Commit Message

BALATON Zoltan May 26, 2024, 11:13 p.m. UTC 
Instead of getting base and adding an offset to it pass pte address to
ppc_hash32_pteg_search() that the only caller of this function already
has and can easily pass it. Also add a local variable in the caller to
avoid getting base multiple times.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 target/ppc/mmu-hash32.c | 31 ++++++++++++++-----------------
 1 file changed, 14 insertions(+), 17 deletions(-)
diff mbox series

Patch

diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c
index cc1e790d0e..6d0adf3357 100644
--- a/target/ppc/mmu-hash32.c
+++ b/target/ppc/mmu-hash32.c
@@ -200,11 +200,10 @@  static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr,
     return false;
 }
 
-static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pteg_off,
+static hwaddr ppc_hash32_pteg_search(PowerPCCPU *cpu, hwaddr pte_addr,
                                      bool secondary, target_ulong ptem,
                                      ppc_hash_pte32_t *pte)
 {
-    hwaddr pte_addr = ppc_hash32_hpt_base(cpu) + pteg_off;
     target_ulong pte0, pte1;
     int i;
 
@@ -245,37 +244,35 @@  static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu,
                                      target_ulong sr, target_ulong eaddr,
                                      ppc_hash_pte32_t *pte)
 {
-    hwaddr pteg_off, pte_addr;
-    hwaddr hash;
+    hwaddr hpt_base, pteg_off, pte_addr, hash;
     uint32_t vsid, pgidx, ptem;
 
+    hpt_base = ppc_hash32_hpt_base(cpu);
     vsid = sr & SR32_VSID;
     pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
     hash = vsid ^ pgidx;
     ptem = (vsid << 7) | (pgidx >> 10);
 
     /* Page address translation */
-    qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx
-            " htab_mask " HWADDR_FMT_plx
-            " hash " HWADDR_FMT_plx "\n",
-            ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash);
+    qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx " htab_mask "
+                  HWADDR_FMT_plx " hash " HWADDR_FMT_plx "\n",
+                  hpt_base, ppc_hash32_hpt_mask(cpu), hash);
 
     /* Primary PTEG lookup */
     qemu_log_mask(CPU_LOG_MMU, "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
-            " vsid=%" PRIx32 " ptem=%" PRIx32
-            " hash=" HWADDR_FMT_plx "\n",
-            ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu),
-            vsid, ptem, hash);
+                  " vsid=%" PRIx32 " ptem=%" PRIx32 " hash=" HWADDR_FMT_plx
+                  "\n", hpt_base, ppc_hash32_hpt_mask(cpu), vsid, ptem, hash);
     pteg_off = get_pteg_offset32(cpu, hash);
-    pte_addr = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte);
+    pte_addr = ppc_hash32_pteg_search(cpu, hpt_base + pteg_off, 0, ptem, pte);
     if (pte_addr == -1) {
         /* Secondary PTEG lookup */
         qemu_log_mask(CPU_LOG_MMU, "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx
-                " vsid=%" PRIx32 " api=%" PRIx32
-                " hash=" HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu),
-                ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash);
+                      " vsid=%" PRIx32 " api=%" PRIx32 " hash=" HWADDR_FMT_plx
+                      "\n", hpt_base, ppc_hash32_hpt_mask(cpu), vsid, ptem,
+                      ~hash);
         pteg_off = get_pteg_offset32(cpu, ~hash);
-        pte_addr = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte);
+        pte_addr = ppc_hash32_pteg_search(cpu, hpt_base + pteg_off, 1, ptem,
+                                          pte);
     }
 
     return pte_addr;