From patchwork Mon Jan 20 01:11:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 312427 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 796232C0086 for ; Mon, 20 Jan 2014 12:12:36 +1100 (EST) Received: from localhost ([::1]:48373 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W53Pk-0004XB-Kg for incoming@patchwork.ozlabs.org; Sun, 19 Jan 2014 20:12:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W53PN-0004EL-0f for qemu-devel@nongnu.org; Sun, 19 Jan 2014 20:12:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W53PH-0003PI-4v for qemu-devel@nongnu.org; Sun, 19 Jan 2014 20:12:08 -0500 Received: from mail-qe0-x22c.google.com ([2607:f8b0:400d:c02::22c]:35835) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W53PH-0003PC-0D for qemu-devel@nongnu.org; Sun, 19 Jan 2014 20:12:03 -0500 Received: by mail-qe0-f44.google.com with SMTP id 1so5860704qee.17 for ; Sun, 19 Jan 2014 17:12:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=UzogHlIRi5QTFs1a106xgbWrI1Nv4XoKf58c5iwc3tU=; b=1Fvtple4PW2YHl2YlCPywzjR4UzqrEhevohdSQvOVOqrtWz61EqYPYdQ1X8I3cnEJz oaAh6vhcyTkoTQgTNcYhTvfH22jIY+P3QlSjjytE/9ii7yunx2DK/hlkeqrHnvzmHuD/ NGq199DQIqW2zQyGDPKGuYk0JGIlGjIjXra+yhA3whUCLUlTDT0eVqeklCjrTsvHMkQM 1uJfJiOtLqxV2t3lRG8up4FzNvQa1bM2C1gHhbH3FRL+h5pAR2JpkFU0nTtwjmIUxyXz jh8Bsa7ctd/qf1E161QOaAiJR5Yimql9e4f9FQcTDfXqV8B0k3kVBi3jeeQiChSUtCbv aWlA== X-Received: by 10.140.20.17 with SMTP id 17mr22662100qgi.28.1390180322694; Sun, 19 Jan 2014 17:12:02 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id ki4sm25721136qeb.0.2014.01.19.17.12.01 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Sun, 19 Jan 2014 17:12:02 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Date: Mon, 20 Jan 2014 11:11:58 +1000 Message-Id: X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c02::22c Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com Subject: [Qemu-devel] [PATCH arm-ccnt v2 1/1] ARM-CCNT: Implements the ARM PMCCNTR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements the ARM PMCCNTR register including the disable and reset components of the PMCR register. Signed-off-by: Alistair Francis --- This patch assumes that non-invasive debugging is not permitted when determing if the counter is disabled V2: Incorperated the comments that Peter Maydell and Peter Crosthwaite had. Now the implementation only required one CPU state target-arm/cpu.h | 3 +++ target-arm/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 198b6b8..2fdab58 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -215,6 +215,9 @@ typedef struct CPUARMState { uint32_t c15_diagnostic; /* diagnostic register */ uint32_t c15_power_diagnostic; uint32_t c15_power_control; /* power control */ + /* If the counter is enabled, this stores the last time the counter + * was reset. Otherwise it stores the counter value */ + uint32_t c15_ccnt; } cp15; /* System registers (AArch64) */ diff --git a/target-arm/helper.c b/target-arm/helper.c index c708f15..8aee764 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -13,6 +13,12 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address, target_ulong *page_size); #endif +/* Definitions for the PMCCNTR and PMCR registers */ +#define PMCRDP 0x20 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -508,6 +514,15 @@ static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &= ~0x39; env->cp15.c9_pmcr |= (value & 0x39); + + if (value & PMCRC || env->cp15.c9_pmcr & PMCRDP || + !(env->cp15.c9_pmcr & PMCRE)) { + /* Store the value of when the reset or disable occured */ + env->cp15.c15_ccnt = ((((qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec())/1000000000) >> 8) & + 0xFFFFFFFF); + } + return 0; } @@ -584,6 +599,32 @@ static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + int64_t total_ticks; + + /* This assumes that non-invasive debugging is not permitted */ + if (env->cp15.c9_pmcr & PMCRDP || + !(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, do not change value */ + *value = env->cp15.c15_ccnt; + return 0; + } + + total_ticks = ((((qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) * + get_ticks_per_sec())/1000000000) >> 8) & 0xFFFFFFFF); + + if (env->cp15.c9_pmcr & PMCRDP) { + /* Increment once every 64 processor clock cycles */ + *value = (uint32_t) (total_ticks - env->cp15.c15_ccnt)/64; + } else { + *value = (uint32_t) (total_ticks - env->cp15.c15_ccnt); + } + + return 0; +} + static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { @@ -644,9 +685,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, - /* Unimplemented, RAZ/WI. XXX PMUSERENR */ { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL1_RW, .readfn = pmccntr_read, + .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), + .resetvalue = 0, .type = ARM_CP_IO }, { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),