From patchwork Sun Sep 14 08:18:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 389015 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A065A14016A for ; Sun, 14 Sep 2014 18:19:16 +1000 (EST) Received: from localhost ([::1]:53288 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XT51e-0003yS-MW for incoming@patchwork.ozlabs.org; Sun, 14 Sep 2014 04:19:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XT514-0002u8-Sc for qemu-devel@nongnu.org; Sun, 14 Sep 2014 04:18:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XT50y-0008AR-Lc for qemu-devel@nongnu.org; Sun, 14 Sep 2014 04:18:38 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:34593) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XT50y-0008AN-9L for qemu-devel@nongnu.org; Sun, 14 Sep 2014 04:18:32 -0400 Received: by mail-pa0-f54.google.com with SMTP id lj1so4417521pab.41 for ; Sun, 14 Sep 2014 01:18:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nOs4LPXEgcjeW9FLmtrtlwitbJuH/Uwxlp2FbH+9WK4=; b=elhOWTn+s1GGUTScFDOgAZo7v7zzeh4hGO3yE2e6qQ/kinyYakC7vq9Ze5mrT1UKzK oVqKKtNjCRgVHGzODR0dx3M/rcDZxXcz4LcxmUKf6lED07qW3YmEShNTsDsoFVm8ks5W D35ECh+3LI2bu3EXKf0m+5ma5amwWALQvoDKBpG6yZslqOYnPbp4rJBGvJjiZKrNyNpm lmyrc3o1TpgknqhnpWW8B0fU/9uzEa7Umu6BzbEdwcPDGov6wNToW6VRTzlDKge0QDBt gGv03DkRIz9tqAbyks8k7TnuEinSMyigXBUd21ttCICcB8qgidg6mVc6agFjOeMgLWCg FAmA== X-Received: by 10.70.64.166 with SMTP id p6mr1400266pds.139.1410682711330; Sun, 14 Sep 2014 01:18:31 -0700 (PDT) Received: from localhost (123-243-147-200.static.tpgi.com.au. [123.243.147.200]) by mx.google.com with ESMTPSA id fl15sm8188019pdb.92.2014.09.14.01.18.29 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 14 Sep 2014 01:18:30 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Sun, 14 Sep 2014 18:18:26 +1000 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::236 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, konstanty@ieee.org, martin.galvan@tallertechnologies.com Subject: [Qemu-devel] [Patch v1 2/8] stm32f205_USART: Add the stm32f205 USART Controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the stm32f205 USART controller (UART also uses the same controller). Signed-off-by: Alistair Francis --- Changes from RFC: - Small changes thanks to Peter C - USART now implements QEMU blocking functions - Split the config settings to device level default-configs/arm-softmmu.mak | 1 + hw/char/Makefile.objs | 1 + hw/char/stm32f205_usart.c | 213 ++++++++++++++++++++++++++++++++++++++ include/hw/char/stm32f205_usart.h | 67 ++++++++++++ 4 files changed, 282 insertions(+) create mode 100644 hw/char/stm32f205_usart.c create mode 100644 include/hw/char/stm32f205_usart.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index cf23b24..422dec0 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -79,6 +79,7 @@ CONFIG_REALVIEW=y CONFIG_ZAURUS=y CONFIG_ZYNQ=y CONFIG_STM32F205_TIMER=y +CONFIG_STM32F205_USART=y CONFIG_VERSATILE_PCI=y CONFIG_VERSATILE_I2C=y diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 317385d..c7b3ce4 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -15,6 +15,7 @@ obj-$(CONFIG_OMAP) += omap_uart.o obj-$(CONFIG_SH4) += sh_serial.o obj-$(CONFIG_PSERIES) += spapr_vty.o obj-$(CONFIG_DIGIC) += digic-uart.o +obj-$(CONFIG_STM32F205_USART) += stm32f205_usart.o common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o diff --git a/hw/char/stm32f205_usart.c b/hw/char/stm32f205_usart.c new file mode 100644 index 0000000..1274e69 --- /dev/null +++ b/hw/char/stm32f205_usart.c @@ -0,0 +1,213 @@ +/* + * STM32F205 USART + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw/char/stm32f205_usart.h" + +#ifndef STM_USART_ERR_DEBUG +#define STM_USART_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (STM_USART_ERR_DEBUG >= lvl) { \ + qemu_log("stm32f205_usart: %s:" fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static int stm32f205_usart_can_receive(void *opaque) +{ + STM32f205UsartState *s = opaque; + + if (s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE && + !(s->usart_sr & USART_SR_RXNE)) { + return 1; + } + + return 0; +} + +static void stm32f205_usart_receive(void *opaque, const uint8_t *buf, int size) +{ + STM32f205UsartState *s = opaque; + + s->usart_dr = *buf; + + s->usart_sr |= USART_SR_RXNE; + + if (s->usart_cr1 & USART_CR1_RXNEIE) { + qemu_set_irq(s->irq, 1); + } + + DB_PRINT("Receiving: %c\n", s->usart_dr); +} + +static void stm32f205_usart_reset(DeviceState *dev) +{ + STM32f205UsartState *s = STM32F205_USART(dev); + + s->usart_sr = 0x00C00000; + s->usart_dr = 0x00000000; + s->usart_brr = 0x00000000; + s->usart_cr1 = 0x00000000; + s->usart_cr2 = 0x00000000; + s->usart_cr3 = 0x00000000; + s->usart_gtpr = 0x00000000; +} + +static uint64_t stm32f205_usart_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32f205UsartState *s = opaque; + uint64_t retvalue; + + DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr); + + switch (addr) { + case USART_SR: + retvalue = s->usart_sr; + s->usart_sr &= ~USART_SR_TC; + if (s->chr) { + qemu_chr_accept_input(s->chr); + } + return retvalue; + case USART_DR: + DB_PRINT("Value: 0x%x, %c\n", s->usart_dr, (char) s->usart_dr); + s->usart_sr |= USART_SR_TXE; + s->usart_sr &= ~USART_SR_RXNE; + return s->usart_dr & 0x3FF; + case USART_BRR: + return s->usart_brr; + case USART_CR1: + return s->usart_cr1; + case USART_CR2: + return s->usart_cr2; + case USART_CR3: + return s->usart_cr3; + case USART_GTPR: + return s->usart_gtpr; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F205_usart_read: Bad offset " \ + "0x%"HWADDR_PRIx"\n", addr); + return 0; + } + + return 0; +} + +static void stm32f205_usart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32f205UsartState *s = opaque; + uint32_t value = val64; + unsigned char ch; + + DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, addr); + + switch (addr) { + case USART_SR: + if (value <= 0x3FF) { + s->usart_sr = value; + } else { + s->usart_sr &= value; + } + return; + case USART_DR: + if (value < 0xF000) { + ch = value; + if (s->chr) { + qemu_chr_fe_write_all(s->chr, &ch, 1); + } + s->usart_sr |= USART_SR_TC; + s->usart_sr &= ~USART_SR_TXE; + } + return; + case USART_BRR: + s->usart_brr = value; + return; + case USART_CR1: + s->usart_cr1 = value; + return; + case USART_CR2: + s->usart_cr2 = value; + return; + case USART_CR3: + s->usart_cr3 = value; + return; + case USART_GTPR: + s->usart_gtpr = value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "STM32F205_usart_write: Bad offset " \ + "0x%"HWADDR_PRIx"\n", addr); + } +} + +static const MemoryRegionOps stm32f205_usart_ops = { + .read = stm32f205_usart_read, + .write = stm32f205_usart_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void stm32f205_usart_init(Object *obj) +{ + STM32f205UsartState *s = STM32F205_USART(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &stm32f205_usart_ops, s, + TYPE_STM32F205_USART, 0x2000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + s->chr = qemu_char_get_next_serial(); + + if (s->chr) { + qemu_chr_add_handlers(s->chr, stm32f205_usart_can_receive, + stm32f205_usart_receive, NULL, s); + } +} + +static void stm32f205_usart_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f205_usart_reset; +} + +static const TypeInfo stm32f205_usart_info = { + .name = TYPE_STM32F205_USART, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32f205UsartState), + .instance_init = stm32f205_usart_init, + .class_init = stm32f205_usart_class_init, +}; + +static void stm32f205_usart_register_types(void) +{ + type_register_static(&stm32f205_usart_info); +} + +type_init(stm32f205_usart_register_types) diff --git a/include/hw/char/stm32f205_usart.h b/include/hw/char/stm32f205_usart.h new file mode 100644 index 0000000..a08cd04 --- /dev/null +++ b/include/hw/char/stm32f205_usart.h @@ -0,0 +1,67 @@ +/* + * STM32F205 USART + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw/sysbus.h" +#include "sysemu/char.h" +#include "hw/hw.h" + +#define USART_SR 0x00 +#define USART_DR 0x04 +#define USART_BRR 0x08 +#define USART_CR1 0x0C +#define USART_CR2 0x10 +#define USART_CR3 0x14 +#define USART_GTPR 0x18 + +#define USART_SR_TXE (1 << 7) +#define USART_SR_TC (1 << 6) +#define USART_SR_RXNE (1 << 5) + +#define USART_CR1_UE (1 << 13) +#define USART_CR1_RXNEIE (1 << 5) +#define USART_CR1_TE (1 << 3) +#define USART_CR1_RE (1 << 2) + +#define TYPE_STM32F205_USART "stm32f205-usart" +#define STM32F205_USART(obj) \ + OBJECT_CHECK(STM32f205UsartState, (obj), TYPE_STM32F205_USART) + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t usart_sr; + uint32_t usart_dr; + uint32_t usart_brr; + uint32_t usart_cr1; + uint32_t usart_cr2; + uint32_t usart_cr3; + uint32_t usart_gtpr; + + CharDriverState *chr; + qemu_irq irq; +} STM32f205UsartState;