From patchwork Tue Jun 24 01:12:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 363276 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2F3DE1400DF for ; Tue, 24 Jun 2014 11:12:59 +1000 (EST) Received: from localhost ([::1]:56906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFI9-0007aO-8K for incoming@patchwork.ozlabs.org; Mon, 23 Jun 2014 21:12:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFHV-0006Oq-51 for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:12:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzFHO-0004uX-86 for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:12:16 -0400 Received: from mail-yk0-x22f.google.com ([2607:f8b0:4002:c07::22f]:54098) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFHO-0004uP-0g for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:12:10 -0400 Received: by mail-yk0-f175.google.com with SMTP id 9so5171153ykp.6 for ; Mon, 23 Jun 2014 18:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=9m6RVbaP4EVIxnG7RRToALO8yPFMjvp0UliElRyE23U=; b=BdkWZtpiYqH6N/TArnWNwdvTio+qP3PFIvOx6Fe628g2SGOoN8FaYo0Hv6dk8bcWPb RaNBVfxlMuQ4JKk2iWQ3ni/VadQQU47jJ/IPkxFmMimAKL0owz6SlIzLibs0ePwc54BY Ex1mBzHDmPSybOIO5XitZvKOWDrqPq1eG0/iPiMtnuGdiXzke3xtEirsw5GkSm8mAC+z PXIxfcPwdVv69iLQIPqdCEXc1dfp+XoMdaU5NY95Qcg/2ne56qUqCo4cmSWyYWrAquF/ /KXhYzHuSGrsFrkv1iPtm4RVga5UD32BC3K7ZlelJzhcdLDIDR1OjWaEKYTyjvatsJIs ELnQ== X-Received: by 10.236.98.103 with SMTP id u67mr39669839yhf.99.1403572329725; Mon, 23 Jun 2014 18:12:09 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id c8sm32308065yho.34.2014.06.23.18.12.06 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 23 Jun 2014 18:12:09 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Tue, 24 Jun 2014 11:12:04 +1000 Message-Id: X-Mailer: git-send-email 1.9.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4002:c07::22f Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v1 3/7] target-arm: Add helper macros and defines for CCNT register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Include a helper function to determine if the CCNT counter is enabled as well as the constants used to mask the pmccfiltr_el0 register. Signed-off-by: Alistair Francis --- target-arm/cpu.h | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6a2efd8..31aa09c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -111,6 +111,25 @@ typedef struct ARMGenericTimer { #define GTIMER_VIRT 1 #define NUM_GTIMERS 2 +#ifndef CONFIG_USER_ONLY + /* Definitions for the PMCCFILTR_EL0 and PMXEVTYPER registers */ + #define PMCP 0x80000000 + #define PMCU 0x40000000 + + /* This implements the PMCCFILTR_EL0:P and U bits; the PMXEVTYPER:P and U + * bits and the c9_pmcr:E bit. + * + * It does not suppor the secure/non-secure componenets of the + * PMCCFILTR_EL0 register + */ + #define CCNT_ENABLED(env) \ + ((env->cp15.c9_pmcr & PMCRE) && \ + !(env->cp15.pmccfiltr_el0 & PMCP && arm_current_pl(env) == 1) && \ + !(env->cp15.pmccfiltr_el0 & PMCU && arm_current_pl(env) == 0) && \ + !(env->cp15.c9_pmxevtyper & PMCP && arm_current_pl(env) == 1) && \ + !(env->cp15.c9_pmxevtyper & PMCU && arm_current_pl(env) == 0)) +#endif + typedef struct CPUARMState { /* Regs for current mode. */ uint32_t regs[16];