From patchwork Fri May 29 06:31:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 477592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CEB87140DED for ; Fri, 29 May 2015 16:33:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Pn5pkJZd; dkim-atps=neutral Received: from localhost ([::1]:33831 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyDqp-0008Nq-07 for incoming@patchwork.ozlabs.org; Fri, 29 May 2015 02:33:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyDqU-0007uT-As for qemu-devel@nongnu.org; Fri, 29 May 2015 02:32:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyDqM-0003zL-0y for qemu-devel@nongnu.org; Fri, 29 May 2015 02:32:42 -0400 Received: from mail-pa0-x232.google.com ([2607:f8b0:400e:c03::232]:34103) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyDqL-0003zB-Mk for qemu-devel@nongnu.org; Fri, 29 May 2015 02:32:33 -0400 Received: by pabru16 with SMTP id ru16so45404213pab.1 for ; Thu, 28 May 2015 23:32:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=GQWdnRvIrhh+cHRnu1bDRfO0X8EA16xamYXSBaNt7kU=; b=Pn5pkJZdilh0Qr5Ae6NeEhgst2BNokaxCDC+CUDgw3V9ncTrSsHTChm0Ib50teI03Q 225Rv//e40eAKU38UYgrWCuDBPf0EMEzMe4DYPtp3moBfmVzfSOf8+Tkixpaw44oNouD Qt6tknYQ/FUMphZvZ3vAAPj1McGZoquI2MvCGSf5Um6lvP0TK3/DwpP8K2uwYfin2zkV +3wXqxc6AeyAssGecRnC/IIEj2sId6oE7QCRqH1bha+3jKWPxG0toWICJuT9H0saZz+p hcHBOO4/EjwpPcsLV69pCyehygBDw3A2avoH0ESPsTvqFs0z2qOyJQLm22tspryGJaE0 Mf8Q== X-Received: by 10.66.119.174 with SMTP id kv14mr12156168pab.5.1432881152998; Thu, 28 May 2015 23:32:32 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id i6sm4381396pde.3.2015.05.28.23.32.31 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Thu, 28 May 2015 23:32:32 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, edgar.iglesias@xilinx.com Date: Fri, 29 May 2015 16:31:58 +1000 Message-Id: X-Mailer: git-send-email 2.1.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::232 Cc: peter.crosthwaite@xilinx.com, rth@twiddle.net, afaerber@suse.de, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v3 5/6] target-microblaze: Convert use-fpu to a CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Originally the use-fpu PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite Reviewed-by: Edgar E. Iglesias --- V3: - Add comments explaing the FPU levels V2: - Remove unnecessary declaration of r Changes since RFC: - Tidy up the if logic hw/microblaze/petalogix_ml605_mmu.c | 7 +++++-- target-microblaze/cpu-qom.h | 1 + target-microblaze/cpu.c | 13 ++++++++++--- target-microblaze/translate.c | 10 +++------- 4 files changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 48c264b..05c120a 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -71,9 +71,8 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu) env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; - env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; + env->pvr.regs[0] |= PVR0_ENDI; env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); - env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; env->pvr.regs[4] = 0xc56b8000; env->pvr.regs[5] = 0xc56be000; } @@ -95,6 +94,10 @@ petalogix_ml605_init(MachineState *machine) /* init CPUs */ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); + /* Use FPU but don't use floating point conversion and square + * root instructions + */ + object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); /* Attach emulated BRAM through the LMB. */ diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index dd04199..a6474f9 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU { struct { bool stackprot; uint32_t base_vectors; + uint8_t usefpu; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0f805d3..b857056 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -110,12 +110,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ - | PVR2_USE_FPU_MASK \ - | PVR2_USE_FPU2_MASK \ | PVR2_FPU_EXC_MASK \ | 0; - env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0; + env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | + (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0); + + env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | + (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); @@ -161,6 +163,11 @@ static Property mb_properties[] = { DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, true), + /* If use-fpu > 0 - FPU is enabled + * If use-fpu = 2 - Floating point conversion and square root instructions + * are enabled + */ + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index bd10b40..8187700 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1411,15 +1411,11 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { - int r; - - r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; - - if (!r && (dc->tb_flags & MSR_EE_FLAG)) { + if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } - return r; + return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK; } static void dec_fpu(DisasContext *dc) @@ -1428,7 +1424,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { + && (dc->cpu->cfg.usefpu != 1)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return;