Message ID | b480032013ffb4688ee013149d43d6ff766100c1.1432879373.git.alistair.francis@xilinx.com |
---|---|
State | New |
Headers | show |
On Fri, May 29, 2015 at 04:31:58PM +1000, Alistair Francis wrote: > Originally the use-fpu PVR bits were manually set for each machine. This > is a hassle and difficult to read, instead set them based on the CPU > properties. The dt bindings for use-fpu are a bit non-intuivie unfortunately... Anyway: Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> > Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> > --- > V3: > - Add comments explaing the FPU levels > V2: > - Remove unnecessary declaration of r > Changes since RFC: > - Tidy up the if logic > > hw/microblaze/petalogix_ml605_mmu.c | 7 +++++-- > target-microblaze/cpu-qom.h | 1 + > target-microblaze/cpu.c | 13 ++++++++++--- > target-microblaze/translate.c | 10 +++------- > 4 files changed, 19 insertions(+), 12 deletions(-) > > diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c > index 48c264b..05c120a 100644 > --- a/hw/microblaze/petalogix_ml605_mmu.c > +++ b/hw/microblaze/petalogix_ml605_mmu.c > @@ -71,9 +71,8 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu) > env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ > /* setup pvr to match kernel setting */ > env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; > - env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; > + env->pvr.regs[0] |= PVR0_ENDI; > env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); > - env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; > env->pvr.regs[4] = 0xc56b8000; > env->pvr.regs[5] = 0xc56be000; > } > @@ -95,6 +94,10 @@ petalogix_ml605_init(MachineState *machine) > > /* init CPUs */ > cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); > + /* Use FPU but don't use floating point conversion and square > + * root instructions > + */ > + object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); > object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); > > /* Attach emulated BRAM through the LMB. */ > diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h > index dd04199..a6474f9 100644 > --- a/target-microblaze/cpu-qom.h > +++ b/target-microblaze/cpu-qom.h > @@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU { > struct { > bool stackprot; > uint32_t base_vectors; > + uint8_t usefpu; > } cfg; > > CPUMBState env; > diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c > index 0f805d3..b857056 100644 > --- a/target-microblaze/cpu.c > +++ b/target-microblaze/cpu.c > @@ -110,12 +110,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > | PVR2_USE_DIV_MASK \ > | PVR2_USE_HW_MUL_MASK \ > | PVR2_USE_MUL64_MASK \ > - | PVR2_USE_FPU_MASK \ > - | PVR2_USE_FPU2_MASK \ > | PVR2_FPU_EXC_MASK \ > | 0; > > - env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0; > + env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | > + (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0); > + > + env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | > + (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); > > env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ > env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); > @@ -161,6 +163,11 @@ static Property mb_properties[] = { > DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), > DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, > true), > + /* If use-fpu > 0 - FPU is enabled > + * If use-fpu = 2 - Floating point conversion and square root instructions > + * are enabled > + */ > + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c > index bd10b40..8187700 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -1411,15 +1411,11 @@ static void dec_rts(DisasContext *dc) > > static int dec_check_fpuv2(DisasContext *dc) > { > - int r; > - > - r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; > - > - if (!r && (dc->tb_flags & MSR_EE_FLAG)) { > + if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { > tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); > t_gen_raise_exception(dc, EXCP_HW_EXCP); > } > - return r; > + return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK; > } > > static void dec_fpu(DisasContext *dc) > @@ -1428,7 +1424,7 @@ static void dec_fpu(DisasContext *dc) > > if ((dc->tb_flags & MSR_EE_FLAG) > && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) > - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { > + && (dc->cpu->cfg.usefpu != 1)) { > tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); > t_gen_raise_exception(dc, EXCP_HW_EXCP); > return; > -- > 1.7.1 >
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 48c264b..05c120a 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -71,9 +71,8 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu) env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; - env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; + env->pvr.regs[0] |= PVR0_ENDI; env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); - env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; env->pvr.regs[4] = 0xc56b8000; env->pvr.regs[5] = 0xc56be000; } @@ -95,6 +94,10 @@ petalogix_ml605_init(MachineState *machine) /* init CPUs */ cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); + /* Use FPU but don't use floating point conversion and square + * root instructions + */ + object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); /* Attach emulated BRAM through the LMB. */ diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index dd04199..a6474f9 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU { struct { bool stackprot; uint32_t base_vectors; + uint8_t usefpu; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0f805d3..b857056 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -110,12 +110,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ - | PVR2_USE_FPU_MASK \ - | PVR2_USE_FPU2_MASK \ | PVR2_FPU_EXC_MASK \ | 0; - env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0; + env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | + (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0); + + env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | + (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); @@ -161,6 +163,11 @@ static Property mb_properties[] = { DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, true), + /* If use-fpu > 0 - FPU is enabled + * If use-fpu = 2 - Floating point conversion and square root instructions + * are enabled + */ + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index bd10b40..8187700 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1411,15 +1411,11 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { - int r; - - r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; - - if (!r && (dc->tb_flags & MSR_EE_FLAG)) { + if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } - return r; + return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK; } static void dec_fpu(DisasContext *dc) @@ -1428,7 +1424,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { + && (dc->cpu->cfg.usefpu != 1)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return;