From patchwork Thu Jan 16 04:31:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 311557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 56CAE2C009A for ; Thu, 16 Jan 2014 15:31:50 +1100 (EST) Received: from localhost ([::1]:58343 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3ecL-0005tj-4C for incoming@patchwork.ozlabs.org; Wed, 15 Jan 2014 23:31:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48116) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3ec0-0005tG-Sp for qemu-devel@nongnu.org; Wed, 15 Jan 2014 23:31:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W3ebu-0001fr-Jx for qemu-devel@nongnu.org; Wed, 15 Jan 2014 23:31:24 -0500 Received: from mail-qe0-x232.google.com ([2607:f8b0:400d:c02::232]:33202) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3ebu-0001fY-ES for qemu-devel@nongnu.org; Wed, 15 Jan 2014 23:31:18 -0500 Received: by mail-qe0-f50.google.com with SMTP id 1so2111413qec.9 for ; Wed, 15 Jan 2014 20:31:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=Ufrq7itnf3sEJ+f+2PywHGDK2hhgHCA4GtrQSVRG+g8=; b=JI1nWgzcbCRmNlWqA0DIthvrunOfkazW6TMX6uXsWcDu/sOfA5KaUVndkJ9dWuY3lM bzNJj9rji3bIMe+2J67hz7OAclgV//DYbQ/4BvmxtWDPfNtjrqhJGnz6l0Jp5rili4G+ VZTUuEQ4C+D3EVacq93T0EkKP9I37oegJaVg1842WjE4MU/44CCM5vHvqgJuhQT9VRct /+PBQ9fTJr+HUT6g6yLqegl0g1zxaic2KEqJhoky9fHJFCFCzw+omhdF5bAamtOrJ068 y9It56tCoyOiTQwv6D66DN4XY2GPF3+Og7cOe3cfNMac+eD0UvAj1C09q6pVDpUPji+O Jpbg== X-Received: by 10.224.124.133 with SMTP id u5mr11433629qar.79.1389846677826; Wed, 15 Jan 2014 20:31:17 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id nz10sm10470788qeb.10.2014.01.15.20.31.16 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Wed, 15 Jan 2014 20:31:17 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Date: Thu, 16 Jan 2014 14:31:13 +1000 Message-Id: X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c02::232 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com Subject: [Qemu-devel] [PATCH arm-ccnt v1 1/1] ARM-CCNT: Implements the ARM PMCCNTR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements the ARM PMCCNTR register including the disable and reset components of the PMCR register. Signed-off-by: Alistair Francis --- This patch assumes that non-invasive debugging is not permitted when determining if the counter is disabled target-arm/cpu.c | 2 ++ target-arm/cpu.h | 3 +++ target-arm/helper.c | 43 ++++++++++++++++++++++++++++++++++++++++--- target-arm/helper.h | 9 +++++++++ 4 files changed, 54 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 52efd5d..a185959 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -76,6 +76,8 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); + env->emm_time = 0; + memset(env, 0, offsetof(CPUARMState, breakpoints)); g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 198b6b8..8c73a56 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -215,8 +215,11 @@ typedef struct CPUARMState { uint32_t c15_diagnostic; /* diagnostic register */ uint32_t c15_power_diagnostic; uint32_t c15_power_control; /* power control */ + uint32_t c15_ccnt; /* Performance Monitors Cycle Count */ } cp15; + int64_t emm_time; /* Used to hold the total emmulation time - in ns */ + /* System registers (AArch64) */ struct { uint64_t tpidr_el0; diff --git a/target-arm/helper.c b/target-arm/helper.c index c708f15..72404cf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -505,9 +505,16 @@ static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) { return EXCP_UDEF; } - /* only the DP, X, D and E bits are writable */ + /* only the DP, X, D and E bits are writeable */ env->cp15.c9_pmcr &= ~0x39; env->cp15.c9_pmcr |= (value & 0x39); + + if (value & PMCRC) { + /* Reset the counter */ + env->emm_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + env->cp15.c15_ccnt = 0; + } + return 0; } @@ -584,6 +591,35 @@ static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + int64_t clock_value; + + /* This assumes that non-invasive debugging is not permitted */ + if (env->cp15.c9_pmcr & PMCRDP || + !(env->cp15.c9_pmcr & PMCRE)) { + /* Counter is disabled, do not change value */ + *value = env->cp15.c15_ccnt; + return 0; + } + + clock_value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + if (env->cp15.c9_pmcr & PMCRDP) { + /* Increment once every 64 processor clock cycles */ + env->cp15.c15_ccnt += (uint32_t) CLOCKNSTOTICKS((clock_value - \ + env->emm_time))/64; + } else { + env->cp15.c15_ccnt += (uint32_t) CLOCKNSTOTICKS((clock_value - \ + env->emm_time)); + } + + env->emm_time = clock_value; + *value = env->cp15.c15_ccnt; + return 0; +} + static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { @@ -644,9 +680,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, - /* Unimplemented, RAZ/WI. XXX PMUSERENR */ { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL1_RW, .readfn = pmccntr_read, + .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), + .resetvalue = 0, .type = ARM_CP_IO }, { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper), diff --git a/target-arm/helper.h b/target-arm/helper.h index 70872df..5b5dc0a 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -492,6 +492,15 @@ DEF_HELPER_3(neon_qzip32, void, env, i32, i32) DEF_HELPER_4(crypto_aese, void, env, i32, i32, i32) DEF_HELPER_4(crypto_aesmc, void, env, i32, i32, i32) +/* Definitions for the PMCCNTR and PMCR registers */ +#define PMCRDP 0x20 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRE 0x1 + +#define CLOCKNSTOTICKS(input) ((((input * get_ticks_per_sec())/1000000000) >> 8) & \ + 0xFFFFFFFF) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif