From patchwork Thu Jun 26 05:02:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 364243 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C19391400AB for ; Thu, 26 Jun 2014 15:06:24 +1000 (EST) Received: from localhost ([::1]:42295 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01t8-0006JT-VJ for incoming@patchwork.ozlabs.org; Thu, 26 Jun 2014 01:06:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01pf-0000ns-8k for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X01pZ-0006r9-8M for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:47 -0400 Received: from mail-ie0-x230.google.com ([2607:f8b0:4001:c03::230]:58704) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01pZ-0006r5-4O for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:41 -0400 Received: by mail-ie0-f176.google.com with SMTP id rd18so2490918iec.7 for ; Wed, 25 Jun 2014 22:02:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=fIJl9/9hkKbUsUAu/hCiPGmSGDAEIJEgx8qNl4hsLuU=; b=jRdaSjCMTnbLSShql9omohQWwE9laaFHeIn5WpKXcl/XzjondzlywkLzubKmaHACGi RqJuQlXBfh8M5ce/Wxw5v5wKWHV/8L4OXhJ1TBxZ76D4DamsCfTIDKHXNWjGkRxJZrnT XbRO+z+4GMb8atYda3OwCTUDzvIfI726TvD8CBDF4xS6K7WIKmR39D8jlVMjevGKxH/w 9DBbzN1Kk/XlPMDtSHgXaomVtQe9eu/GfbVFymSTcIpbquUEXNp9sUfZZ1NiD8774tmt 9DD7xR2ekgreFFdRQzDa43Fw8UORE4Pc01aH6ZZmvzdcRoNXL9bqmq/xYCZtllgjRLGl OZSQ== X-Received: by 10.50.77.34 with SMTP id p2mr1325178igw.31.1403758960592; Wed, 25 Jun 2014 22:02:40 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id vl10sm1055809igb.16.2014.06.25.22.02.37 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Wed, 25 Jun 2014 22:02:40 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org Date: Thu, 26 Jun 2014 15:02:34 +1000 Message-Id: X-Mailer: git-send-email 1.9.0 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c03::230 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, cov@codeaurora.org, alistair.francis@xilinx.com Subject: [Qemu-devel] [PATCH v2 5/7] target-arm: Remove old code and replace with new functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Remove the old PMCCNTR code and replace it with calls to the new pmccntr_sync() function and the CCNT_ENABLED macro Signed-off-by: Alistair Francis --- target-arm/helper.c | 27 ++++----------------------- 1 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 016fe47..0bd00cb 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -609,20 +609,7 @@ void pmccntr_sync(CPUARMState *env) static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t temp_ticks; - - temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), - get_ticks_per_sec(), 1000000); - - if (env->cp15.c9_pmcr & PMCRE) { - /* If the counter is enabled */ - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt; - } else { - env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; - } - } + pmccntr_sync(env); if (value & PMCRC) { /* The counter has been reset */ @@ -633,20 +620,14 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.c9_pmcr &= ~0x39; env->cp15.c9_pmcr |= (value & 0x39); - if (env->cp15.c9_pmcr & PMCRE) { - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - temp_ticks /= 64; - } - env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; - } + pmccntr_sync(env); } static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { uint64_t total_ticks; - if (!(env->cp15.c9_pmcr & PMCRE)) { + if (!arm_ccnt_enabled(env)) { /* Counter is disabled, do not change value */ return env->cp15.c15_ccnt; } @@ -666,7 +647,7 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, { uint64_t total_ticks; - if (!(env->cp15.c9_pmcr & PMCRE)) { + if (!arm_ccnt_enabled(env)) { /* Counter is disabled, set the absolute value */ env->cp15.c15_ccnt = value; return;