From patchwork Mon Sep 24 09:18:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 186344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E45A92C008A for ; Mon, 24 Sep 2012 19:21:38 +1000 (EST) Received: from localhost ([::1]:48487 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TG4rB-00080n-1t for incoming@patchwork.ozlabs.org; Mon, 24 Sep 2012 05:21:37 -0400 Received: from eggs.gnu.org ([208.118.235.92]:35659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TG4pu-0005vL-Kn for qemu-devel@nongnu.org; Mon, 24 Sep 2012 05:20:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TG4po-00035Z-Gw for qemu-devel@nongnu.org; Mon, 24 Sep 2012 05:20:18 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:51281) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TG4po-00034W-Ag for qemu-devel@nongnu.org; Mon, 24 Sep 2012 05:20:12 -0400 Received: by padfb10 with SMTP id fb10so1348114pad.4 for ; Mon, 24 Sep 2012 02:20:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=CMaHgYWq/V0YGrXt6ewUBpBUbum8YBvNyqAJka+YF0c=; b=ptkfQSDl7/tKId64AGzJWNN09T+LQ6p0Ow51QJHC75vQp2ZNcqpO4914cmfoDZWp7d VsbQxVv9bJPlNgb5vScrfwh9DtC/iGD3dgfKI/tUWlpbZWkV0moZCyi/hldTI33EdmDm gUGVeauGdSXVEkqVP5Ql6AwTYo9IBr8gY/DcmrPPGgVvA7w0X5j8laNSmj0FJfWgwp0y 6zyHLyCmNsR5kF6rs68ErmQ6wAlbOJPQHe/ZuCTvbfGCCj2sew8NqcDy//jMvhqRYbML ozyz3pqb4GrEpa95t02wuo4osTw9feel3+TkWPzXR0k9u1vXUyaM6VYB+sRymejG34wC mGFA== Received: by 10.68.200.162 with SMTP id jt2mr34921897pbc.54.1348478409913; Mon, 24 Sep 2012 02:20:09 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id s10sm8477703paz.11.2012.09.24.02.20.06 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 24 Sep 2012 02:20:09 -0700 (PDT) From: "Peter A. G. Crosthwaite" To: qemu-devel@nongnu.org, paul@codesourcery.com, edgar.iglesias@gmail.com, peter.maydell@linaro.org, stefanha@gmail.com Date: Mon, 24 Sep 2012 19:18:42 +1000 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQmzzAqdXAFxCJ9Bx4spUShd/lU/M5ay7zpsrsTK61jvQ4DOX0drF9aEypMnfCojMeO1vdbm X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: blauwirbel@gmail.com, "Peter A. G. Crosthwaite" , i.mitsyanko@samsung.com Subject: [Qemu-devel] [PATCH v7 12/13] xilinx_zynq: Added SPI controllers + flashes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added the two SPI controllers to the zynq machine model. Attached two SPI flash devices to each controller. Signed-off-by: Peter A. G. Crosthwaite --- hw/xilinx_zynq.c | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 7e6c273..e273711 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -24,6 +24,9 @@ #include "flash.h" #include "blockdev.h" #include "loader.h" +#include "ssi.h" + +#define NUM_SPI_FLASHES 2 #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) @@ -46,6 +49,34 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } +static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq) +{ + DeviceState *dev; + SysBusDevice *busdev; + SSIBus *spi; + int i; + + dev = qdev_create(NULL, "xilinx,spips"); + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, base_addr); + sysbus_connect_irq(busdev, 0, irq); + + spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); + + for (i = 0; i < NUM_SPI_FLASHES; ++i) { + qemu_irq cs_line; + + dev = ssi_create_slave_no_init(spi, "m25p80"); + qdev_prop_set_string(dev, "partname", (char *)"n25q128"); + qdev_init_nofail(dev); + + cs_line = qdev_get_gpio_in(dev, 0); + sysbus_connect_irq(busdev, i+1, cs_line); + } + +} + static void zynq_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -113,6 +144,9 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, pic[n] = qdev_get_gpio_in(dev, n); } + zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]); + zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]); + sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);