diff mbox series

答复: [PATCH] hw/net: cadence_gem: fix: type2_compare_x_word_0 error

Message ID KL1PR0601MB4891516AF3BF1C93D4ED6372E3C72@KL1PR0601MB4891.apcprd06.prod.outlook.com
State New
Headers show
Series 答复: [PATCH] hw/net: cadence_gem: fix: type2_compare_x_word_0 error | expand

Commit Message

Andrew.Yuan June 11, 2024, 6:24 a.m. UTC 
OK，I will send another patch for the missing logic for the DISABLE_MASK bit;


发件人: Edgar E. Iglesias <edgar.iglesias@gmail.com>
发送时间: 2024年6月6日 19:04
收件人: andrew Yuan <andrew.yuan@jaguarmicro.com>
抄送: luc.michel@amd.com; alistair@alistair23.me; peter.maydell@linaro.org; jasowang@redhat.com; qemu-arm@nongnu.org; qemu-devel@nongnu.org
主题: Re: [PATCH] hw/net: cadence_gem: fix: type2_compare_x_word_0 error

External Mail: This email originated from OUTSIDE of the organization!
Do not click links, open attachments or provide ANY information unless you recognize the sender and know the content is safe.

On Thu, Jun 6, 2024 at 12:00 PM Andrew.Yuan <andrew.yuan@jaguarmicro.com<mailto:andrew.yuan@jaguarmicro.com>> wrote:
        In the Cadence IP for Gigabit Ethernet MAC Part Number: IP7014 IP Rev: R1p12 - Doc Rev: 1.3 User Guide, the specification for the type2_compare_x_word_0 register is as follows:
        The byte stored in bits [23:16] is compared against the byte in the received frame from the selected offset+0, and the byte stored in bits [31:24] is compared against the byte in
        the received frame from the selected offset+1.

        However, there is an implementation error in the cadence_gem model in qemu：
        the byte stored in bits [31:24] is compared against the byte in the received frame from the selected offset+0

        Now, the error code is as follows:
        rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];

        and needs to be corrected to：
        rx_cmp = rxbuf_ptr[offset + 1] << 8 | rxbuf_ptr[offset];

Signed-off-by: Andrew.Yuan <andrew.yuan@jaguarmicro.com<mailto:andrew.yuan@jaguarmicro.com>>


LGTM:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com<mailto:edgar.iglesias@amd.com>>

At some point it would be nice to add the missing logic for the DISABLE_MASK bit that
extends the compare range from 16 to 32-bits.

Cheers,
Edgar


---
 hw/net/cadence_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
2.37.0.windows.1
diff mbox series

Patch

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index ec7bf562e5..9c73ded0d3 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -946,7 +946,7 @@  static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
                 break;
             }

-            rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
+            rx_cmp = rxbuf_ptr[offset + 1] << 8 | rxbuf_ptr[offset];
             mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
             compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);