From patchwork Sun Oct 4 11:11:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 526096 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 30F4E1402B2 for ; Sun, 4 Oct 2015 22:11:39 +1100 (AEDT) Received: from localhost ([::1]:42058 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZihCb-0000hB-4W for incoming@patchwork.ozlabs.org; Sun, 04 Oct 2015 07:11:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZihCJ-0000MM-NV for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:11:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZihCG-0002bo-Gv for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:11:19 -0400 Received: from col004-omc2s17.hotmail.com ([65.55.34.91]:57762) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZihCG-0002bi-6m for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:11:16 -0400 Received: from COL130-W69 ([65.55.34.72]) by COL004-OMC2S17.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.23008); Sun, 4 Oct 2015 04:11:15 -0700 X-TMN: [30hjZR7GRBoQqpsJDtAAWW2cr3jOOqpp] X-Originating-Email: [xili_gchen_5257@hotmail.com] Message-ID: From: Chen Gang To: "rth@twiddle.net" , Peter Maydell , Chris Metcalf Date: Sun, 4 Oct 2015 19:11:15 +0800 Importance: Normal MIME-Version: 1.0 X-OriginalArrivalTime: 04 Oct 2015 11:11:15.0642 (UTC) FILETIME=[62E3C1A0:01D0FE95] X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 65.55.34.91 Cc: qemu-devel Subject: [Qemu-devel] [PATCH v2] target-tilegx: Implement v?int_* instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From 418c1600c481f0acbde42987db286b48f1848399 Mon Sep 17 00:00:00 2001 From: Chen Gang Date: Fri, 2 Oct 2015 11:00:37 +0800 Subject: [PATCH v2] target-tilegx: Implement v?int_* instructions. Signed-off-by: Chen Gang ---  target-tilegx/helper.h      |  5 ++++  target-tilegx/simd_helper.c | 56 +++++++++++++++++++++++++++++++++++++++++++++  target-tilegx/translate.c   | 14 ++++++++++++  3 files changed, 75 insertions(+) --  1.9.3 diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h index 82d84f1..c58ee20 100644 --- a/target-tilegx/helper.h +++ b/target-tilegx/helper.h @@ -10,6 +10,11 @@ DEF_HELPER_FLAGS_3(cmula, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)  DEF_HELPER_FLAGS_3(cmulaf, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)  DEF_HELPER_FLAGS_4(cmul2, TCG_CALL_NO_RWG_SE, i64, i64, i64, int, int)   +DEF_HELPER_FLAGS_2(v1int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v1int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2int_h, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2int_l, TCG_CALL_NO_RWG_SE, i64, i64, i64) +  DEF_HELPER_FLAGS_2(v1multu, TCG_CALL_NO_RWG_SE, i64, i64, i64)  DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)  DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c index 23c20bd..6fa6318 100644 --- a/target-tilegx/simd_helper.c +++ b/target-tilegx/simd_helper.c @@ -102,3 +102,59 @@ uint64_t helper_v2shrs(uint64_t a, uint64_t b)      }      return r;  } + +uint64_t helper_v1int_h(uint64_t a, uint64_t b) +{ +    uint64_t r = 0, tmp; +    int i; + +    for (i = 0; i < 32; i += 8) { +        tmp = (uint8_t)(a>> (i + 32)); +        r |= tmp << (2 * i + 8); +        tmp = (uint8_t)(b>> (i + 32)); +        r |= tmp << 2 * i; +    } +    return r; +} + +uint64_t helper_v1int_l(uint64_t a, uint64_t b) +{ +    uint64_t r = 0, tmp; +    int i; + +    for (i = 0; i < 32; i += 8) { +        tmp = (uint8_t)(a>> i); +        r |= tmp << (2 * i + 8); +        tmp = (uint8_t)(b>> i); +        r |= tmp << 2 * i; +    } +    return r; +} + +uint64_t helper_v2int_h(uint64_t a, uint64_t b) +{ +    uint64_t r = 0, tmp; +    int i; + +    for (i = 0; i < 32; i += 16) { +        tmp = (uint16_t)(a>> (i + 32)); +        r |= tmp << (2 * i + 16); +        tmp = (uint16_t)(b>> (i + 32)); +        r |= tmp << 2 * i; +    } +    return r; +} + +uint64_t helper_v2int_l(uint64_t a, uint64_t b) +{ +    uint64_t r = 0, tmp; +    int i; + +    for (i = 0; i < 32; i += 16) { +        tmp = (uint16_t)(a>> i); +        r |= tmp << (2 * i + 16); +        tmp = (uint16_t)(b>> i); +        r |= tmp << 2 * i; +    } +    return r; +} diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 9bb8857..034cbc2 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1260,10 +1260,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,      case OE_RRR(V1DOTPUS, 0, X0):      case OE_RRR(V1DOTPU, 0, X0):      case OE_RRR(V1DOTP, 0, X0): +        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;      case OE_RRR(V1INT_H, 0, X0):      case OE_RRR(V1INT_H, 0, X1): +        gen_helper_v1int_h(tdest, tsrca, tsrcb); +        mnemonic = "v1int_h"; +        break;      case OE_RRR(V1INT_L, 0, X0):      case OE_RRR(V1INT_L, 0, X1): +        gen_helper_v1int_l(tdest, tsrca, tsrcb); +        mnemonic = "v1int_l"; +        break;      case OE_RRR(V1MAXU, 0, X0):      case OE_RRR(V1MAXU, 0, X1):      case OE_RRR(V1MINU, 0, X0): @@ -1329,10 +1336,17 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,      case OE_RRR(V2CMPNE, 0, X1):      case OE_RRR(V2DOTPA, 0, X0):      case OE_RRR(V2DOTP, 0, X0): +        return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;      case OE_RRR(V2INT_H, 0, X0):      case OE_RRR(V2INT_H, 0, X1): +        gen_helper_v2int_h(tdest, tsrca, tsrcb); +        mnemonic = "v2int_h"; +        break;      case OE_RRR(V2INT_L, 0, X0):      case OE_RRR(V2INT_L, 0, X1): +        gen_helper_v2int_l(tdest, tsrca, tsrcb); +        mnemonic = "v2int_l"; +        break;      case OE_RRR(V2MAXS, 0, X0):      case OE_RRR(V2MAXS, 0, X1):      case OE_RRR(V2MINS, 0, X0):