From patchwork Sun Oct 4 11:15:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 526100 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4151B1402B4 for ; Sun, 4 Oct 2015 22:16:15 +1100 (AEDT) Received: from localhost ([::1]:42085 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZihH3-0005MZ-Cb for incoming@patchwork.ozlabs.org; Sun, 04 Oct 2015 07:16:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58658) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZihGb-0004gl-8e for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:15:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZihGW-0004ab-6Z for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:15:45 -0400 Received: from col004-omc2s13.hotmail.com ([65.55.34.87]:61542) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZihGV-0004aW-OJ for qemu-devel@nongnu.org; Sun, 04 Oct 2015 07:15:40 -0400 Received: from COL130-W40 ([65.55.34.71]) by COL004-OMC2S13.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.23008); Sun, 4 Oct 2015 04:15:39 -0700 X-TMN: [HpwOFv9zPlQQ7eYBAA17SvUxqx81cW0B] X-Originating-Email: [xili_gchen_5257@hotmail.com] Message-ID: From: Chen Gang To: "rth@twiddle.net" , Peter Maydell , Chris Metcalf Date: Sun, 4 Oct 2015 19:15:38 +0800 Importance: Normal MIME-Version: 1.0 X-OriginalArrivalTime: 04 Oct 2015 11:15:39.0155 (UTC) FILETIME=[FFF4A630:01D0FE95] X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 65.55.34.87 Cc: qemu-devel Subject: [Qemu-devel] [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From 40ec3f1c75b4c97e3e0495c9e465be898f48a652 Mon Sep 17 00:00:00 2001 From: Chen Gang Date: Sun, 4 Oct 2015 17:34:17 +0800 Subject: [PATCH] target-tilegx: Let prefetch nop instructions return before allocating dest temporary register Or it will cause issue by the dest temporary registers. Signed-off-by: Chen Gang ---  target-tilegx/translate.c | 85 +++++++++++++++++++++++++----------------------  1 file changed, 46 insertions(+), 39 deletions(-) --  1.9.3 diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index acb9ec4..2913902 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -496,7 +496,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,      const char *mnemonic;      TCGMemOp memop;      TileExcp ret = TILEGX_EXCP_NONE; -    bool prefetch_nofault = false;        /* Eliminate instructions with no output before doing anything else.  */      switch (opext) { @@ -597,6 +596,26 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,          }          qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);          return ret; + +    case OE_RR_X1(LD1U): +        memop = MO_UB; +        mnemonic = "ld1u"; /* prefetch, prefetch_l1 */ +        goto do_load_nofault; +    case OE_RR_X1(LD2U): +        memop = MO_TEUW; +        mnemonic = "ld2u"; /* prefetch_l2 */ +        goto do_load_nofault; +    case OE_RR_X1(LD4U): +        memop = MO_TEUL; +        mnemonic = "ld4u"; /* prefetch_l3 */ +    do_load_nofault: +        if (dest != TILEGX_R_ZERO) { +            tcg_gen_qemu_ld_tl(dest_gr(dc, dest), load_gr(dc, srca), +                               dc->mmuidx, memop); +        } +        qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, +                      reg_names[dest], reg_names[srca]); +        return ret;      }        tdest = dest_gr(dc, dest); @@ -620,29 +639,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,          memop = MO_SB;          mnemonic = "ld1s"; /* prefetch_l1_fault */          goto do_load; -    case OE_RR_X1(LD1U): -        memop = MO_UB; -        mnemonic = "ld1u"; /* prefetch, prefetch_l1 */ -        prefetch_nofault = (dest == TILEGX_R_ZERO); -        goto do_load;      case OE_RR_X1(LD2S):          memop = MO_TESW;          mnemonic = "ld2s"; /* prefetch_l2_fault */          goto do_load; -    case OE_RR_X1(LD2U): -        memop = MO_TEUW; -        mnemonic = "ld2u"; /* prefetch_l2 */ -        prefetch_nofault = (dest == TILEGX_R_ZERO); -        goto do_load;      case OE_RR_X1(LD4S):          memop = MO_TESL;          mnemonic = "ld4s"; /* prefetch_l3_fault */          goto do_load; -    case OE_RR_X1(LD4U): -        memop = MO_TEUL; -        mnemonic = "ld4u"; /* prefetch_l3 */ -        prefetch_nofault = (dest == TILEGX_R_ZERO); -        goto do_load;      case OE_RR_X1(LDNT1S):          memop = MO_SB;          mnemonic = "ldnt1s"; @@ -675,9 +679,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,          memop = MO_TEQ;          mnemonic = "ld";      do_load: -        if (!prefetch_nofault) { -            tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); -        } +        tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);          break;      case OE_RR_X1(LDNA):          tcg_gen_andi_tl(tdest, tsrca, ~7); @@ -1472,15 +1474,36 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,  static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,                                 unsigned dest, unsigned srca, int imm)  { -    TCGv tdest = dest_gr(dc, dest); +    TCGv tdest;      TCGv tsrca = load_gr(dc, srca); -    bool prefetch_nofault = false;      const char *mnemonic;      TCGMemOp memop;      int i2, i3;      TCGv t0;        switch (opext) { +    case OE_IM(LD1U_ADD, X1): +        memop = MO_UB; +        mnemonic = "ld1u_add"; /* prefetch_add_l1 */ +        goto do_load_add_nofault; +    case OE_IM(LD2U_ADD, X1): +        memop = MO_TEUW; +        mnemonic = "ld2u_add"; /* prefetch_add_l2 */ +        goto do_load_add_nofault; +    case OE_IM(LD4U_ADD, X1): +        memop = MO_TEUL; +        mnemonic = "ld4u_add"; /* prefetch_add_l3 */ +    do_load_add_nofault: +        if (dest != TILEGX_R_ZERO) { +            tcg_gen_qemu_ld_tl(dest_gr(dc, dest), tsrca, dc->mmuidx, memop); +        } +        tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm); +        goto done2; +    } + +    tdest = dest_gr(dc, dest); + +    switch (opext) {      case OE(ADDI_OPCODE_Y0, 0, Y0):      case OE(ADDI_OPCODE_Y1, 0, Y1):      case OE_IM(ADDI, X0): @@ -1526,29 +1549,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,          memop = MO_SB;          mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */          goto do_load_add; -    case OE_IM(LD1U_ADD, X1): -        memop = MO_UB; -        mnemonic = "ld1u_add"; /* prefetch_add_l1 */ -        prefetch_nofault = (dest == TILEGX_R_ZERO); -        goto do_load_add;      case OE_IM(LD2S_ADD, X1):          memop = MO_TESW;          mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */          goto do_load_add; -    case OE_IM(LD2U_ADD, X1): -        memop = MO_TEUW; -        mnemonic = "ld2u_add"; /* prefetch_add_l2 */ -        prefetch_nofault = (dest == TILEGX_R_ZERO); -        goto do_load_add;      case OE_IM(LD4S_ADD, X1):          memop = MO_TESL;          mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */          goto do_load_add; -    case OE_IM(LD4U_ADD, X1): -        memop = MO_TEUL; -        mnemonic = "ld4u_add"; /* prefetch_add_l3 */ -        prefetch_nofault = (dest == TILEGX_R_ZERO); -        goto do_load_add;      case OE_IM(LDNT1S_ADD, X1):          memop = MO_SB;          mnemonic = "ldnt1s_add"; @@ -1581,9 +1589,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,          memop = MO_TEQ;          mnemonic = "ld_add";      do_load_add: -        if (!prefetch_nofault) { -            tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); -        } +        tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);          tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);          break;      case OE_IM(LDNA_ADD, X1): @@ -1756,6 +1762,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,          return TILEGX_EXCP_OPCODE_UNKNOWN;      }   +done2:      qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,                    reg_names[dest], reg_names[srca], imm);      return TILEGX_EXCP_NONE;