Message ID | AANLkTik42D9KkUk1gLxG7h36g91a_uD2Q_bRL-Q9xxIr@mail.gmail.com |
---|---|
State | New |
Headers | show |
2010/7/12 Blue Swirl <blauwirbel@gmail.com>: > Use pci_bar_map() instead of a mapping function. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > hw/isa.h | 1 + > hw/isa_mmio.c | 17 +++++++++++++++-- > hw/sun4u.c | 29 ++++++++++------------------- > 3 files changed, 26 insertions(+), 21 deletions(-) > > diff --git a/hw/isa.h b/hw/isa.h > index aaf0272..6fba4ac 100644 > --- a/hw/isa.h > +++ b/hw/isa.h > @@ -33,6 +33,7 @@ ISADevice *isa_create_simple(const char *name); > extern target_phys_addr_t isa_mem_base; > > void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be); > +int pci_isa_mmio_init(int be); > > /* dma.c */ > int DMA_get_channel_mode (int nchan); > diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c > index 66bdd2c..3b2de4a 100644 > --- a/hw/isa_mmio.c > +++ b/hw/isa_mmio.c > @@ -125,7 +125,7 @@ static CPUReadMemoryFunc * const isa_mmio_read_le[] = { > > static int isa_mmio_iomemtype = 0; > > -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) > +static int isa_mmio_memtype(int be) > { > if (!isa_mmio_iomemtype) { > if (be) { > @@ -138,5 +138,18 @@ void isa_mmio_init(target_phys_addr_t base, > target_phys_addr_t size, int be) > NULL); > } > } > - cpu_register_physical_memory(base, size, isa_mmio_iomemtype); > + return isa_mmio_iomemtype; > +} > + > +void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) > +{ > + int isa; > + > + isa = isa_mmio_memtype(be); > + cpu_register_physical_memory(base, size, isa); > +} > + > +int pci_isa_mmio_init(int be) > +{ > + return isa_mmio_memtype(be); > } > diff --git a/hw/sun4u.c b/hw/sun4u.c > index 31c0c4c..8565243 100644 > --- a/hw/sun4u.c > +++ b/hw/sun4u.c > @@ -517,21 +517,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) > } > } > > -static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, > - pcibus_t addr, pcibus_t size, int type) > -{ > - EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n", > - region_num, addr); > - switch (region_num) { > - case 0: > - isa_mmio_init(addr, 0x1000000, 1); > - break; > - case 1: > - isa_mmio_init(addr, 0x800000, 1); > - break; > - } > -} > - > static void dummy_isa_irq_handler(void *opaque, int n, int level) > { > } > @@ -550,6 +535,8 @@ pci_ebus_init(PCIBus *bus, int devfn) > static int > pci_ebus_init1(PCIDevice *s) > { > + int io_index; > + > isa_bus_new(&s->qdev); > > pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); > @@ -563,10 +550,14 @@ pci_ebus_init1(PCIDevice *s) > pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); > s->config[0x0D] = 0x0a; // latency_timer > > - pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, > - ebus_mmio_mapfunc); > - pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, > - ebus_mmio_mapfunc); > + pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, NULL); > + io_index = pci_isa_mmio_init(1); > + pci_bar_map(s, 0, 0, 0, 0x1000000, io_index); > + > + pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, NULL); > + io_index = pci_isa_mmio_init(1); > + pci_bar_map(s, 1, 0, 0, 0x800000, io_index); Are these well-known constants? > + > return 0; > } > > -- > 1.7.1 > >
On Mon, Jul 12, 2010 at 7:03 PM, Artyom Tarasenko <atar4qemu@googlemail.com> wrote: > 2010/7/12 Blue Swirl <blauwirbel@gmail.com>: >> Use pci_bar_map() instead of a mapping function. >> >> Signed-off-by: Blue Swirl <blauwirbel@gmail.com> >> --- >> hw/isa.h | 1 + >> hw/isa_mmio.c | 17 +++++++++++++++-- >> hw/sun4u.c | 29 ++++++++++------------------- >> 3 files changed, 26 insertions(+), 21 deletions(-) >> >> diff --git a/hw/isa.h b/hw/isa.h >> index aaf0272..6fba4ac 100644 >> --- a/hw/isa.h >> +++ b/hw/isa.h >> @@ -33,6 +33,7 @@ ISADevice *isa_create_simple(const char *name); >> extern target_phys_addr_t isa_mem_base; >> >> void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be); >> +int pci_isa_mmio_init(int be); >> >> /* dma.c */ >> int DMA_get_channel_mode (int nchan); >> diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c >> index 66bdd2c..3b2de4a 100644 >> --- a/hw/isa_mmio.c >> +++ b/hw/isa_mmio.c >> @@ -125,7 +125,7 @@ static CPUReadMemoryFunc * const isa_mmio_read_le[] = { >> >> static int isa_mmio_iomemtype = 0; >> >> -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) >> +static int isa_mmio_memtype(int be) >> { >> if (!isa_mmio_iomemtype) { >> if (be) { >> @@ -138,5 +138,18 @@ void isa_mmio_init(target_phys_addr_t base, >> target_phys_addr_t size, int be) >> NULL); >> } >> } >> - cpu_register_physical_memory(base, size, isa_mmio_iomemtype); >> + return isa_mmio_iomemtype; >> +} >> + >> +void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) >> +{ >> + int isa; >> + >> + isa = isa_mmio_memtype(be); >> + cpu_register_physical_memory(base, size, isa); >> +} >> + >> +int pci_isa_mmio_init(int be) >> +{ >> + return isa_mmio_memtype(be); >> } >> diff --git a/hw/sun4u.c b/hw/sun4u.c >> index 31c0c4c..8565243 100644 >> --- a/hw/sun4u.c >> +++ b/hw/sun4u.c >> @@ -517,21 +517,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) >> } >> } >> >> -static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, >> - pcibus_t addr, pcibus_t size, int type) >> -{ >> - EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n", >> - region_num, addr); >> - switch (region_num) { >> - case 0: >> - isa_mmio_init(addr, 0x1000000, 1); >> - break; >> - case 1: >> - isa_mmio_init(addr, 0x800000, 1); >> - break; >> - } >> -} >> - >> static void dummy_isa_irq_handler(void *opaque, int n, int level) >> { >> } >> @@ -550,6 +535,8 @@ pci_ebus_init(PCIBus *bus, int devfn) >> static int >> pci_ebus_init1(PCIDevice *s) >> { >> + int io_index; >> + >> isa_bus_new(&s->qdev); >> >> pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); >> @@ -563,10 +550,14 @@ pci_ebus_init1(PCIDevice *s) >> pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); >> s->config[0x0D] = 0x0a; // latency_timer >> >> - pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, >> - ebus_mmio_mapfunc); >> - pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, >> - ebus_mmio_mapfunc); >> + pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, NULL); >> + io_index = pci_isa_mmio_init(1); >> + pci_bar_map(s, 0, 0, 0, 0x1000000, io_index); >> + >> + pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, NULL); >> + io_index = pci_isa_mmio_init(1); >> + pci_bar_map(s, 1, 0, 0, 0x800000, io_index); > > Are these well-known constants? IIRC I picked them from device tree range sizes: ranges: 00000010.00000000.82010810.00000000.f0000000.01000000.00000014.00000000.82010814.00000000.f1000000.00800000 It's a bit annoying to repeat the constants, but this is a simple case where the subregion size is equal to the whole BAR size.
diff --git a/hw/isa.h b/hw/isa.h index aaf0272..6fba4ac 100644 --- a/hw/isa.h +++ b/hw/isa.h @@ -33,6 +33,7 @@ ISADevice *isa_create_simple(const char *name); extern target_phys_addr_t isa_mem_base; void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be); +int pci_isa_mmio_init(int be); /* dma.c */ int DMA_get_channel_mode (int nchan); diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c index 66bdd2c..3b2de4a 100644 --- a/hw/isa_mmio.c +++ b/hw/isa_mmio.c @@ -125,7 +125,7 @@ static CPUReadMemoryFunc * const isa_mmio_read_le[] = { static int isa_mmio_iomemtype = 0; -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) +static int isa_mmio_memtype(int be) { if (!isa_mmio_iomemtype) { if (be) { @@ -138,5 +138,18 @@ void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) NULL); } } - cpu_register_physical_memory(base, size, isa_mmio_iomemtype); + return isa_mmio_iomemtype; +} + +void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be) +{ + int isa; + + isa = isa_mmio_memtype(be); + cpu_register_physical_memory(base, size, isa); +} + +int pci_isa_mmio_init(int be) +{ + return isa_mmio_memtype(be); } diff --git a/hw/sun4u.c b/hw/sun4u.c index 31c0c4c..8565243 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -517,21 +517,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) } } -static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, - pcibus_t addr, pcibus_t size, int type) -{ - EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n", - region_num, addr); - switch (region_num) { - case 0: - isa_mmio_init(addr, 0x1000000, 1); - break; - case 1: - isa_mmio_init(addr, 0x800000, 1); - break; - } -} - static void dummy_isa_irq_handler(void *opaque, int n, int level) { } @@ -550,6 +535,8 @@ pci_ebus_init(PCIBus *bus, int devfn) static int pci_ebus_init1(PCIDevice *s) { + int io_index; + isa_bus_new(&s->qdev); pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); @@ -563,10 +550,14 @@ pci_ebus_init1(PCIDevice *s) pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); s->config[0x0D] = 0x0a; // latency_timer - pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, - ebus_mmio_mapfunc); - pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, - ebus_mmio_mapfunc); + pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, NULL); + io_index = pci_isa_mmio_init(1); + pci_bar_map(s, 0, 0, 0, 0x1000000, io_index); + + pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, NULL); + io_index = pci_isa_mmio_init(1); + pci_bar_map(s, 1, 0, 0, 0x800000, io_index); + return 0; }
Use pci_bar_map() instead of a mapping function. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> --- hw/isa.h | 1 + hw/isa_mmio.c | 17 +++++++++++++++-- hw/sun4u.c | 29 ++++++++++------------------- 3 files changed, 26 insertions(+), 21 deletions(-)