From patchwork Thu May 17 02:28:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yang Z" X-Patchwork-Id: 159804 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 56B3DB6FAF for ; Thu, 17 May 2012 12:56:23 +1000 (EST) Received: from localhost ([::1]:47539 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUqTQ-0005s0-K2 for incoming@patchwork.ozlabs.org; Wed, 16 May 2012 22:29:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:47737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUqSl-0004BR-DI for qemu-devel@nongnu.org; Wed, 16 May 2012 22:29:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SUqSj-0007h8-GU for qemu-devel@nongnu.org; Wed, 16 May 2012 22:29:10 -0400 Received: from mga14.intel.com ([143.182.124.37]:62544) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUqSj-0007fy-6T for qemu-devel@nongnu.org; Wed, 16 May 2012 22:29:09 -0400 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 16 May 2012 19:29:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="144183537" Received: from azsmsx601.amr.corp.intel.com ([10.2.121.193]) by azsmga001.ch.intel.com with ESMTP; 16 May 2012 19:29:08 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by azsmsx601.amr.corp.intel.com (10.2.121.193) with Microsoft SMTP Server (TLS) id 8.2.255.0; Wed, 16 May 2012 19:29:07 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.6]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.90]) with mapi id 14.01.0355.002; Thu, 17 May 2012 10:28:59 +0800 From: "Zhang, Yang Z" To: "'qemu-devel@nongnu.org'" Thread-Topic: [PATCH v6 4/7] RTC: Add divider reset support Thread-Index: Ac0z1NCnhM4lthsPRNizt9VB4FEqYA== Date: Thu, 17 May 2012 02:28:59 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 143.182.124.37 Cc: 'Paolo Bonzini' , "'aliguori@us.ibm.com'" , "'qemu-devel@nongnu.org'" Subject: [Qemu-devel] [PATCH v6 4/7] RTC: Add divider reset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The first update cycle begins one - half seconds later when divider reset is removing. Signed-off-by: Yang Zhang --- hw/mc146818rtc.c | 46 ++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 40 insertions(+), 6 deletions(-) -- 1.7.1 diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index b03c420..3dd71ac 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -80,6 +80,14 @@ static void rtc_set_time(RTCState *s); static void rtc_calibrate_time(RTCState *s); static void rtc_set_cmos(RTCState *s); +static int32_t divider_reset; + +static inline bool rtc_running(RTCState *s) +{ + return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && + (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); +} + static uint64_t get_guest_rtc_us(RTCState *s) { uint64_t guest_rtc; @@ -221,12 +229,30 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) case RTC_YEAR: s->cmos_data[s->cmos_index] = data; /* if in set mode, do not update the time */ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_set_time(s); rtc_set_offset(s, 1, 0); } break; case RTC_REG_A: + if (((data & 0x60) == 0x60) && + (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { + rtc_calibrate_time(s); + rtc_set_cmos(s); + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + s->old_guest_usec = get_guest_rtc_us(s); + } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && + (data & 0x70) <= 0x20) { + /* when the divider reset is removed, the first update cycle + * begins one-half second later*/ + divider_reset = 1; + if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + rtc_set_time(s); + rtc_set_offset(s, 0, 1); + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + divider_reset = 0; + } + } /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); @@ -235,7 +261,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) case RTC_REG_B: if (data & REG_B_SET) { /* update cmos to when the rtc was stopping */ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_calibrate_time(s); rtc_set_cmos(s); s->old_guest_usec = get_guest_rtc_us(s); @@ -245,9 +271,16 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) data &= ~REG_B_UIE; } else { /* if disabling set mode, update the time */ - if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && + (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { rtc_set_time(s); - rtc_set_offset(s, 0, 0); + if (divider_reset == 1) { + rtc_set_offset(s, 0, 1); + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + divider_reset = 0; + } else { + rtc_set_offset(s, 0, 0); + } } } s->cmos_data[RTC_REG_B] = data; @@ -348,7 +381,8 @@ static int update_in_progress(RTCState *s) { int64_t guest_usec; - if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + if ((s->cmos_data[RTC_REG_B] & REG_B_SET) || + ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60)) { return 0; } guest_usec = get_guest_rtc_us(s); @@ -376,7 +410,7 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) case RTC_YEAR: /* if not in set mode, calibrate cmos before * reading*/ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_calibrate_time(s); rtc_set_cmos(s); }