From patchwork Fri Mar 2 06:59:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yang Z" X-Patchwork-Id: 144144 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E4FF8B6F98 for ; Fri, 2 Mar 2012 18:02:33 +1100 (EST) Received: from localhost ([::1]:40358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3MVb-0002SZ-MH for incoming@patchwork.ozlabs.org; Fri, 02 Mar 2012 02:02:31 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3MV0-0001cW-Gp for qemu-devel@nongnu.org; Fri, 02 Mar 2012 02:02:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S3MUy-0007oS-MC for qemu-devel@nongnu.org; Fri, 02 Mar 2012 02:01:54 -0500 Received: from mga03.intel.com ([143.182.124.21]:18299) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3MUy-0007ny-FC for qemu-devel@nongnu.org; Fri, 02 Mar 2012 02:01:52 -0500 Received: from azsmga002.ch.intel.com ([10.2.17.35]) by azsmga101.ch.intel.com with ESMTP; 01 Mar 2012 23:01:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="72669908" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by AZSMGA002.ch.intel.com with ESMTP; 01 Mar 2012 23:01:48 -0800 Received: from pgsmsx103.gar.corp.intel.com (10.221.44.82) by PGSMSX102.gar.corp.intel.com (10.221.44.80) with Microsoft SMTP Server (TLS) id 14.1.355.2; Fri, 2 Mar 2012 15:00:01 +0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by PGSMSX103.gar.corp.intel.com (10.221.44.82) with Microsoft SMTP Server (TLS) id 14.1.355.2; Fri, 2 Mar 2012 15:00:01 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.142]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.91]) with mapi id 14.01.0355.002; Fri, 2 Mar 2012 15:00:00 +0800 From: "Zhang, Yang Z" To: "qemu-devel@nongnu.org" Thread-Topic: [PATCH v3 4/7] RTC: Set internal millisecond register to 500ms when reset divider Thread-Index: Acz4QhOuUzYcGZZ7QOaKz3ieVNeblg== Date: Fri, 2 Mar 2012 06:59:59 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 143.182.124.21 Cc: Paolo Bonzini , "aliguori@us.ibm.com" , Marcelo Tosatti , Jan Kiszka , "kvm@vger.kernel.org" Subject: [Qemu-devel] [PATCH v3 4/7] RTC: Set internal millisecond register to 500ms when reset divider X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The first update cycle begins one - half seconds later when divider reset is removing. Signed-off-by: Yang Zhang --- hw/mc146818rtc.c | 38 +++++++++++++++++++++++++++++++++----- 1 files changed, 33 insertions(+), 5 deletions(-) -- 1.7.1 diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 6ebb8f6..5e7fbb5 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -110,6 +110,8 @@ static void rtc_set_time(RTCState *s); static void rtc_calibrate_time(RTCState *s); static void rtc_set_cmos(RTCState *s); +static int32_t divider_reset; + static uint64_t get_guest_rtc_us(RTCState *s) { int64_t host_usec, offset_usec, guest_usec; @@ -220,16 +222,24 @@ static void rtc_periodic_timer(void *opaque) } } -static void rtc_set_offset(RTCState *s) +static void rtc_set_offset(RTCState *s, int32_t start_usec) { struct tm *tm = &s->current_tm; - int64_t host_usec, guest_sec, guest_usec; + int64_t host_usec, guest_sec, guest_usec, offset_usec, old_guest_usec; host_usec = qemu_get_clock_ns(host_clock) / NS_PER_USEC; + offset_usec = s->offset_sec * USEC_PER_SEC + s->offset_usec; + old_guest_usec = (host_usec + offset_usec) % USEC_PER_SEC; guest_sec = mktimegm(tm); - guest_usec = guest_sec * USEC_PER_SEC; + /* start_usec equal 0 means rtc internal millisecond is + * same with before */ + if (start_usec == 0) { + guest_usec = guest_sec * USEC_PER_SEC + old_guest_usec; + } else { + guest_usec = guest_sec * USEC_PER_SEC + start_usec; + } s->offset_sec = (guest_usec - host_usec) / USEC_PER_SEC; s->offset_usec = (guest_usec - host_usec) % USEC_PER_SEC; } @@ -260,10 +270,22 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) /* if in set mode, do not update the time */ if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { rtc_set_time(s); - rtc_set_offset(s); + rtc_set_offset(s, 0); } break; case RTC_REG_A: + /* when the divider reset is removed, the first update cycle + * begins one-half second later*/ + if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && + ((data & 0x70) >> 4) <= 2) { + divider_reset = 1; + if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + rtc_calibrate_time(s); + rtc_set_offset(s, 500000); + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + divider_reset = 0; + } + } /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); @@ -283,7 +305,13 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) /* if disabling set mode, update the time */ if (s->cmos_data[RTC_REG_B] & REG_B_SET) { rtc_set_time(s); - rtc_set_offset(s); + if (divider_reset == 1) { + rtc_set_offset(s, 500000); + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + divider_reset = 0; + } else { + rtc_set_offset(s, 0); + } } } s->cmos_data[RTC_REG_B] = data;