From patchwork Mon Feb 20 00:25:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yang Z" X-Patchwork-Id: 142092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2FC4EB6FA5 for ; Mon, 20 Feb 2012 11:26:12 +1100 (EST) Received: from localhost ([::1]:59169 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzH4y-0001R2-6s for incoming@patchwork.ozlabs.org; Sun, 19 Feb 2012 19:26:08 -0500 Received: from eggs.gnu.org ([140.186.70.92]:47336) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzH4m-0001IL-Ky for qemu-devel@nongnu.org; Sun, 19 Feb 2012 19:25:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RzH4l-0007Qy-Fb for qemu-devel@nongnu.org; Sun, 19 Feb 2012 19:25:56 -0500 Received: from mga11.intel.com ([192.55.52.93]:47490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RzH4l-0007Qo-BH for qemu-devel@nongnu.org; Sun, 19 Feb 2012 19:25:55 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 19 Feb 2012 16:25:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="127226687" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by fmsmga002.fm.intel.com with ESMTP; 19 Feb 2012 16:25:52 -0800 Received: from pgsmsx152.gar.corp.intel.com (172.30.236.43) by PGSMSX102.gar.corp.intel.com (10.221.44.80) with Microsoft SMTP Server (TLS) id 14.1.355.2; Mon, 20 Feb 2012 08:25:52 +0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by PGSMSX152.gar.corp.intel.com (172.30.236.43) with Microsoft SMTP Server (TLS) id 14.1.355.2; Mon, 20 Feb 2012 08:25:51 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.142]) by SHSMSX102.ccr.corp.intel.com ([169.254.2.36]) with mapi id 14.01.0355.002; Mon, 20 Feb 2012 08:25:50 +0800 From: "Zhang, Yang Z" To: "qemu-devel@nongnu.org" Thread-Topic: [PATCH v2 4/4] RTC:Add UIP(update in progress) check logic Thread-Index: AczvZjHW86RajID0TpKJ4QV9Kcm2IQ== Date: Mon, 20 Feb 2012 00:25:50 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Cc: Paolo Bonzini , "aliguori@us.ibm.com" , Marcelo Tosatti , Jan Kiszka , "kvm@vger.kernel.org" Subject: [Qemu-devel] [PATCH v2 4/4] RTC:Add UIP(update in progress) check logic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The UIP(update in progress) is set when RTC is updating. We only consider the normal oscillator(32Khz) mode. When time base is 32kHz, the update cycle takes 1984us at the end of every second. And the update cycle begins 244us later after UIP is set. So the UIP is set in 2228us at end of every second. Signed-off-by: Yang Zhang --- hw/mc146818rtc.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) -- 1.7.1 diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 2445c6b..d4be8e9 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -601,6 +601,29 @@ static void rtc_calibrate_time(RTCState *s) s->current_tm = *ret; } +static int update_in_progress(RTCState *s) +{ + struct timeval tv_now; + int64_t host_usec, offset_usec, guest_usec; + + if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + return 0; + } + + gettimeofday(&tv_now, NULL); + host_usec = tv_now.tv_sec * USEC_PER_SEC + tv_now.tv_usec; + offset_usec = s->offset_sec * USEC_PER_SEC + s->offset_usec; + guest_usec = host_usec + offset_usec; + + /* UIP bit will be set at last 2228us of every second. + * Only consider oscillator in 32.768kHz*/ + if ((guest_usec % USEC_PER_SEC) >= (USEC_PER_SEC - 2228)) { + return 1; + } + + return 0; +} + static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) { RTCState *s = opaque; @@ -622,6 +645,9 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) break; case RTC_REG_A: ret = s->cmos_data[s->cmos_index]; + if (update_in_progress(s)) { + ret |= REG_A_UIP; + } break; case RTC_REG_C: ret = s->cmos_data[s->cmos_index];